Introducing jitter to a switching frequency by way of modulating current limit

Patent metadata

Field	Value
Publication number	US-9774248-B2
Application number	US-201514881527-A
Country	US
Kind code	B2
Filing date	Oct 13, 2015
Priority date	Nov 10, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A controller for use in a power converter includes a switch controller coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a drain current through the power switch. The switch controller is coupled to generate a drive signal to control switching of the power switch in response to the current sense signal and a modulated current limit signal to control a transfer of energy from an input to an output of the power converter. A current limit generator is coupled to generate a current limit signal. A jitter generator is coupled to generate a jitter signal. An arithmetic operator circuit is coupled to generate the modulated current limit signal in response to the current limit signal and the jitter signal.

First claim

What is claimed is:

1. A controller for use in a power converter, comprising:
a switch controller coupled to a power switch coupled to an energy transfer element, wherein the switch controller is coupled to receive a current sense signal representative of a drain current through the power switch, wherein the switch controller is coupled to generate a drive signal to control switching of the power switch in response to the current sense signal and a modulated current limit signal to control a transfer of energy from an input of the power converter to an output of the power converter;
a current limit generator coupled to generate a current limit signal;
a jitter generator coupled to generate a jitter signal, wherein the jitter signal is a periodic signal having a modulation time period that is greater than a switching period of the drive signal; and
an arithmetic operator circuit coupled to receive the current limit signal and the jitter signal, wherein the arithmetic operator circuit is coupled to generate the modulated current limit signal in response to the current limit signal and the jitter signal.

2. The controller of claim 1 wherein the wherein the modulated current limit signal is a product of the current limit signal and the jitter signal.

3. The controller of claim 1 wherein the switch controller is further coupled to receive an enable signal from an enable circuit coupled to receive a feedback signal representative of an output quantity of the power converter, wherein switch controller is coupled to generate the drive signal in response to the current sense signal, the modulated current limit signal, and the enable signal.

4. The controller of claim 3 wherein the feedback signal representative of the output quantity of the power converter is coupled to be generated by a sense circuit coupled to sense the output quantity of the power converter.

5. The controller of claim 3 wherein the drive signal is coupled to turn off the power switch in response to a comparison of the current sense signal and the modulated current limit signal, and wherein the drive signal is coupled to turn on the power switch in response to the enable signal.

6. The controller of claim 3 wherein the switch controller includes a flip-flop circuit coupled to generate the drive signal, wherein the flip-flop circuit is coupled to be reset in response to a comparison of the current sense signal and the modulated current limit signal, and wherein the flip-flop circuit is coupled to be set in response to the enable signal.

7. The controller of claim 3 wherein the enable circuit is coupled to generate the enable signal to cause a duration of an off time of the power switch to be substantially constant.

8. The controller of claim 7 wherein a duration of an on time of the power switch is variable such that a switching period of the power switch 110 is variable.

9. The controller of claim 1 wherein the jitter signal is a sawtooth waveform signal having a modulation time period that is greater than a switching period of the drive signal.

10. The controller of claim 9 wherein the sawtooth waveform signal is coupled to oscillate between a peak value and a bottom value.

11. The controller of claim 10 wherein the modulated current limit signal ( 238 ) is a product of the current limit signal and the jitter signal, wherein an average of the peak value and the bottom value is substantially equal to a unity multiplier for the jitter signal when determining the product of the current limit signal and the jitter signal.

12. The controller of claim 1 wherein the jitter signal is a stepladder waveform signal having a modulation time period that is greater than a switching period of the drive signal.

13. The controller of claim 12 wherein the stepladder waveform signal is coupled to oscillate between a peak value and a bottom value.

14. The controller of claim 13 wherein the modulated current limit signal is a product of the current limit signal and the jitter signal, wherein an average of the peak value and the bottom value is substantially equal to a unity multiplier for the jitter signal when determining the product of the current limit signal and the jitter signal.

15. The controller of claim 1 wherein the current limit signal is a constant signal.

16. The controller of claim 1 wherein the current limit signal is a variable signal during an on time of the power switch.

17. The controller of claim 16 wherein the current limit signal is coupled to decrease during the on time of the power switch.

18. The controller of claim 1 wherein an on time of the drive signal is coupled to vary in response to the modulated current limit signal.

19. The controller of claim 1 wherein an off time of the drive signal is coupled to vary in response to the modulated current limit signal.

20. The controller of claim 1 wherein the switch controller is coupled to reduce audio noise generated by the switching of the power switch in response to the modulated current limit signal.

Assignees

• Power Integrations Inc

Inventors

• Saint-Pierre Roland Sylvere
• Pham Giao Minh
• Wong Lance M
• Matthews David Michael Hugh

Classifications

• H02M1/44 Primary

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M3/33507

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title