Semiconductor device

Patent metadata

Field	Value
Publication number	US-9773767-B2
Application number	US-201514850339-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	May 30, 2013
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A semiconductor device includes an insulating substrate including an insulating plate and a circuit plate disposed on a main surface of the insulating plate; a semiconductor chip having a front surface provided with an electrode and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate and including a metal layer; a conductive post having one end electrically and mechanically connected to the electrode and another end electrically and mechanically connected to the metal layer; a passive element fixed to the printed circuit board; and a plurality of positioning posts fixed to the printed circuit board to position the passive element.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating substrate including an insulating plate and a circuit plate disposed on a main surface of the insulating plate;
a semiconductor chip having a front surface provided with an electrode and a rear surface fixed to the circuit plate;
a printed circuit board facing the insulating substrate and including a metal layer;
a conductive post having one end electrically and mechanically connected to the electrode, and another end electrically and mechanically connected to the metal layer;
a passive element fixed to the printed circuit board; and
a plurality of positioning posts formed from a conductor and fixed to the printed circuit board to position the passive element, at least one positioning post of the plurality of positioning posts being integrally formed with the conductive post.

2. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a switching element.

3. The semiconductor device according to claim 2 , wherein the passive element includes a capacitor for suppressing a variation in a control voltage of the semiconductor chip.

4. The semiconductor device according to claim 2 , wherein the passive element includes a resistor for adjusting a control timing of the semiconductor chip.

5. The semiconductor device according to claim 1 , further comprising an insulating resin covering the semiconductor chip, the circuit plate, and the printed circuit board.

6. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises a plurality of semiconductor chips forming an upper arm and a lower arm, and
the passive element is electrically connected to the semiconductor chip forming the upper arm or the semiconductor chip forming the lower arm.

Assignees

• Fuji Electric Co Ltd

Inventors

• Nakamura Yoko
• Nashida Norihiro

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title