Solder bump cleaning before reflow

US9773744B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9773744-B2
Application numberUS-201113181111-A
CountryUS
Kind codeB2
Filing dateJul 12, 2011
Priority dateJul 12, 2011
Publication dateSep 26, 2017
Grant dateSep 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an oxide film from a surface of the solder bump, and, after removing the oxide film, performing a solder bump reflow process in a reducing ambient to reflow the solder bump.

First claim

Opening claim text (preview).

What is claimed: 1. A method, comprising: forming a solder bump above a metallization layer of a semiconductor device, wherein forming said solder bump comprises embedding a portion of said solder bump in a passivation layer that is formed above said metallization layer; after forming said solder bump, removing an oxide film from a surface of said solder bump by performing a wet chemical cleaning process; and after removing said oxide film, performing a solder bump reflow process in a reducing ambient to reflow said solder bump into a solder ball. 2. The method of claim 1 , wherein performing said solder bump reflow process in said reducing ambient comprises performing said solder bump reflow process in an ambient comprising formic acid. 3. The method of claim 1 , further comprising exposing said surface of said solder bump to an oxidizing ambient prior to removing said oxide film. 4. The method of claim 1 , wherein performing said wet chemical cleaning process comprises exposing said surface of said solder bump to an acid solution comprising one of methanesulfonic acid, formic acid, nitric acid and hydrochloric acid. 5. The method of claim 1 , wherein performing said wet chemical cleaning process comprises using an acid solution having a molar concentration in the range of approximately 0.05M to 4.0M. 6. The method of claim 1 , wherein performing said wet chemical cleaning process comprises exposing said surface of said solder bump to said acid solution for a time ranging from approximately 15 seconds to approximately 330 seconds. 7. The method of claim 1 , wherein performing said wet chemical cleaning process comprises exposing said surface of said solder bump to an acid solution comprising one of formic acid and hydrochloric acid, said acid solution having a molar concentration in the range of approximately 0.3M to 0.5M. 8. The method of claim 7 , wherein performing said wet chemical cleaning process comprises exposing said surface of said solder bump to said acid solution for a time ranging from approximately 20 second to approximately 120 seconds. 9. A method, comprising: forming a solder bump above a last metallization layer formed above a semiconductor device, wherein forming said solder bump comprises embedding a portion of said solder bump in a passivation layer that is formed above said last metallization layer; after forming said solder bump, exposing said solder bump to an oxygen-containing environment; after exposing said solder bump to said oxygen-containing environment, exposing said solder bump to a wet chemical cleaning process to substantially remove a native oxide film from said surface of said solder bump; and after exposing said solder bump to said wet chemical cleaning process, reflowing said solder bump in a reflow ambient comprising formic acid so as to transform said solder bump into a solder ball. 10. The method of claim 9 , wherein said native oxide film forms on said surface of said solder bump during said exposure to said oxygen-containing environment. 11. The method of claim 9 , wherein exposing said solder bump to a wet chemical cleaning process comprises exposing said solder bump to an acid solution comprising one of formic acid and hydrochloric acid, said acid solution having a molar concentration in the range of approximately 0.3M to 0.5M. 12. The method of claim 11 , wherein exposing said solder bump to said wet chemical cleaning process comprises exposing said surface of said solder bump to said acid solution for a time ranging from approximately 20 second to approximately 120 seconds. 13. The method of claim 9 , wherein forming said solder bump comprises forming said solder bump from a substantially lead-free material comprising at least one of tin, silver and copper. 14. The method of claim 13 , wherein forming said solder bump from a substantially lead-free material comprises forming said solder bump from an alloy comprising tin and approximately 1.8 to 3.0 weight percent silver. 15. A method, comprising: forming a substantially lead-free solder bump above an underbump metallization layer of a semiconductor device; after forming said solder bump, performing a wet chemical cleaning process to remove an oxide film from a surface of said solder bump by exposing said solder bump to an acid solution comprising one of formic acid and hydrochloric acid, wherein said wet chemical cleaning process is performed prior to performing any reflow processes on said solder bump; and after performing said wet chemical cleaning process, performing a reflow process to reflow said solder bump into a solder ball, wherein said reflow process is performed in an ambient comprising formic acid. 16. The method of claim 15 , wherein said oxide film forms on said surface of said solder bump when said solder bump is exposed to an ambient comprising oxygen. 17. The method of claim 15 , wherein said reflow process is performed within approximately 12 hours after performing said wet chemical cleaning process. 18. The method of claim 1 , wherein said reflow process is performed prior to performing a flip-chip operation to bond a semiconductor chip comprising said semiconductor device to a carrier substrate. 19. The method of claim 9 , wherein reflowing said solder bump is performed prior to performing a flip-chip operation to bond a semiconductor chip comprising said semiconductor device to a carrier substrate. 20. A method, comprising: forming a solder bump above a last metallization layer formed above a semiconductor device; exposing said solder bump to an oxygen-containing environment, wherein a native oxide film is formed on said solder bump during said exposure of said solder bump to said oxygen-containing environment; exposing said solder bump to a wet chemical cleaning process to substantially remove said native oxide film from said surface of said solder bump, wherein said solder bump is exposed to said wet chemical cleaning process prior to performing any reflow processes on said solder bump; after exposing said solder bump to said wet chemical cleaning process and prior to performing any reflow processes on said solder bump, forming an additional native oxide film on said surface of said solder bump; after forming said additional native oxide film, reflowing said solder bump in a reflow ambient comprising formic acid so as to transform said solder bump into a solder ball; and removing said additional native oxide film from said surface of said solder bump while reflowing said solder bump.

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What does patent US9773744B2 cover?
Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an…
Who is the assignee on this patent?
Willeke Reiner, Zenner Sören, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification B23K1/0016. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Sep 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).