Pixel circuit with organic light emitting diode

Patent metadata

Field	Value
Publication number	US-9773449-B2
Application number	US-201414558777-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Sep 24, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A pixel circuit with an organic light emitting diode (OLED) compensates a threshold voltage of the driving switch therein by controlling the connection relationship between a first capacitor and a second capacitor therein. As such, the compensation time of the pixel circuit may be different from the data writing time of the same. Also, the capacitance to be written with the data may be less than that in the conventional technique so that the time needed for the data writing is then reduced and the pixel circuit in the present invention can be used in a display device with a high refresh rate.

First claim

What is claimed is:

1. A pixel circuit, comprising:
an organic light emitting diode (OLED) having a first terminal and a second terminal, the first terminal of the OLED receiving a first reference voltage, and the OLED being driven by a driving current;
a driving switch having a first terminal, a second terminal, and a control terminal, the first terminal of the driving switch receiving a second reference voltage, and the control terminal of the driving switch being controlled by a driving voltage to provide the driving current;
an enabling switch having two terminals which electrically connect to the second terminal of the driving switch and the second terminal of the OLED respectively, and configured to be off during an entire first time period in a working period and be on during an entire second time period following the first time period in the working period;
a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor electrically connecting to the control terminal of the driving switch, and the second terminal of the first capacitor receiving a third reference voltage;
a second capacitor having a first terminal and a second terminal, and the first terminal of the second capacitor electrically connecting to the control terminal of the driving switch; and
a compensation module, configured to supply the third reference voltage to the control terminal of the driving switch during an entire third time period in the first time period, electrically connect the control terminal of the driving switch to the second terminal of the driving switch during an entire fourth time period following the third time period in the first time period, supply a data voltage to the second terminal of the second capacitor during an entire fifth time period following the third time period in the first time period, and make the second terminal of the second capacitor receive the third reference voltage during the entire second time period;
wherein the fifth time period partially overlaps and is shorter than the fourth time period.

2. The pixel circuit according to claim 1 , wherein the compensation module comprising:
a data switch having a first terminal and a second terminal, the first terminal of the data switch receiving the data voltage, the second terminal of the data switch electrically connecting to the second terminal of the second capacitor, the data switch being turned on during the entire fifth time period and being turned off during the working period except the fifth time period;
a first switch having two terminals that receive the third reference voltage and are electrically connected to the control terminal of the driving switch respectively, and configured to be on during the entire third time period and be off during the working period except the third time period;
a second switch having two terminals that are electrically connected to the second terminal of the driving switch and the control terminal of the driving switch respectively, and configured to be on during the entire fourth time period and be off during the working period except the fourth time period; and
a third switch having two terminals that are electrically connected to the second terminal of the data switch and receive the third reference voltage respectively, and configured to be on during the entire second time period.

3. The pixel circuit according to claim 2 , wherein the first reference voltage is equal to the third reference voltage.

4. The pixel circuit according to claim 2 , wherein the fourth time period is longer than or equal to the fifth time period.

5. The pixel circuit according to claim 4 , wherein the fourth time period and the fifth time period end synchronously.

6. The pixel circuit according to claim 2 , wherein a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is a natural number.

7. The pixel circuit according to claim 6 , wherein the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

8. The pixel circuit according to claim 6 , wherein the first capacitor comprises first sub-capacitors, the second capacitor comprises second sub-capacitors, and the first sub-capacitor and the second sub-capacitors are arranged around a common centroid.

9. The pixel circuit according to claim 1 , wherein the driving switch and the enabling switch are P type transistors, and the first reference voltage and the third reference voltage are lower than the second reference voltage.

10. The pixel circuit according to claim 9 , wherein the first reference voltage is equal to the third reference voltage.

11. The pixel circuit according to claim 9 , wherein the fourth time period is longer than or equal to the fifth time period.

12. The pixel circuit according to claim 11 , wherein the fourth time period and the fifth time period end synchronously.

13. The pixel circuit according to claim 9 , wherein a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is a natural number.

14. The pixel circuit according to claim 13 , wherein the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

15. The pixel circuit according to claim 13 , wherein the first capacitor comprises first sub-capacitors, the second capacitor comprises second sub-capacitors, and the first sub-capacitor and the second sub-capacitors are arranged around a common centroid.

16. The pixel circuit according to claim 1 , wherein the driving switch and the enabling switch are N type transistors, and the first reference voltage and the third reference voltage are lower than the second reference voltage.

17. The pixel circuit according to claim 16 , wherein the first reference voltage is equal to the third reference voltage.

18. The pixel circuit according to claim 16 , wherein the fourth time period is longer than or equal to the fifth time period.

19. The pixel circuit according to claim 18 , wherein the fourth time period and the fifth time period end simultaneously.

20. The pixel circuit according to claim 16 , wherein a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is a natural number.

21. The pixel circuit according to claim 20 , wherein the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

22. The pixel circuit according to claim 20 , wherein the first capacitor comprises first sub-capacitors, the second capacitor comprises second sub-capacitors, and the first sub-capacitor and the second sub-capacitors are arranged around a common centroid.

23. The pixel circuit according to claim 1 , wherein the first reference voltage is equal to the third reference voltage.

24. The pixel circuit according to claim 1 , wherein the fourth time period is longer than or equal to the fifth time period.

25. The pixel circuit according to claim 24 , wherein the fourth time period and the fifth time period end simultaneously.

26. The pixel circuit according to claim 1 , wherein a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is a natural number.

27. The pixel circuit according to claim 26 , wherein the capacitance value of the first capacitor is equal to the capacitance value of the second

Assignees

• Au Optronics Corp
• Au Optronics Corp

Inventors

• Lin Yung-Ming
• Yeh Chia-Yuan

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title