System and method for operating system aware low latency interrupt handling

Patent metadata

Field	Value
Publication number	US-9772960-B2
Application number	US-201213649762-A
Country	US
Kind code	B2
Filing date	Oct 11, 2012
Priority date	Oct 11, 2012
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

First claim

What is claimed is:

1. A non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, results in a performance of the following:
executing an operating system within a kernel critical section, wherein executing within the kernel critical section includes masking out a second priority level interrupt request;
executing a fast interrupt handler in a user mode when the operating system is within the kernel critical section, wherein the user mode includes a software interrupt instruction that can be utilized by the fast interrupt handler to request a kernel service;
receiving, by the fast interrupt handler, a fast interrupt request asserted by a hardware device when the operating system is within the kernel critical section, wherein the fast interrupt request includes a request to invoke a kernel service that corresponds to the second priority level interrupt request;
raising, by the fast interrupt handler through the software interrupt instruction when the operating system is within the kernel critical section, the request to invoke the kernel service that corresponds to the second priority level interrupt request;
deferring invocation of the kernel service that corresponds to the second priority level interrupt request to avoid invoking the kernel service that corresponds to the second priority level interrupt request until after the operating system has exited the kernel critical section; and
processing the second priority level interrupt request after the operating system exited the kernel critical section.

2. The non-transitory computer readable storage medium of claim 1 , wherein the execution of the set of instructions further results in the performance of the following:
after the operating system has exited the kernel critical section continuing to execute the fast interrupt handler in the user mode to service the hardware device.

3. The non-transitory computer readable storage medium of claim 1 , wherein the second priority level interrupt request is a regular interrupt request (“IRQ”).

4. The non-transitory computer readable storage medium of claim 1 , wherein the execution of the set of instructions further results in the performance of the following:
queuing the requested kernel service that corresponds to the second priority level interrupt request onto a buffer; and
managing the buffer with a lockless increment of reader and writer indices.

5. The non-transitory computer readable storage medium of claim 1 , wherein the processor is a component within a reduced instruction set computer (“RISC”) instruction set architecture (“ISA”).

6. The non-transitory computer readable storage medium of claim 1 , wherein the user mode includes a dedicated set of registers that can be utilized by the fast interrupt handler.

7. The non-transitory computer readable storage medium of claim 1 , wherein the operating system is a real-time operating system (“RTOS”).

8. The non-transitory computer readable storage medium of claim 1 , wherein processing the second priority level interrupt request includes enabling the second priority level interrupt request.

9. A system, comprising:
a processor executing an operating system within a kernel critical section, wherein executing within the kernel critical section includes masking out a second priority level interrupt request;
executing a fast interrupt handler in a user mode when the operating system is within the kernel critical section, wherein the user mode includes a software interrupt instruction that can be utilized by the fast interrupt handler to request a kernel service;
receiving, by the fast interrupt handler, a fast interrupt request asserted by a hardware device when the operating system is within the kernel critical section, wherein the fast interrupt request includes a request to invoke a kernel service that corresponds to the second priority level interrupt request;
raising, by the fast interrupt handler through the software interrupt instruction when the operating system is within the kernel critical section, the request to invoke the kernel service that corresponds to the second priority level interrupt request;
deferring invocation of the kernel service that corresponds to the second priority level interrupt request to avoid invoking the kernel service that corresponds to the second priority level interrupt request until after the operating system has exited the kernel critical section; and
processing the second priority level interrupt request after the operating system exited the kernel critical section.

10. The system of claim 9 , wherein after the operating system has exited the kernel critical section continuing to execute the fast interrupt handler in the user mode to service the hardware device.

11. The system of claim 9 , wherein the second priority level is a regular interrupt request (“IRQ”).

12. The system of claim 9 , wherein the processor queues the requested kernel service that corresponds to the second priority level interrupt request onto a buffer, and manages the buffer with a lockless increment of reader and writer indices.

13. A method of updating an address table, comprising:
executing an operating system within a kernel critical section, wherein executing within the kernel critical section includes masking out a second priority level interrupt request;
executing a fast interrupt handler in a user mode when the operating system is within the kernel critical section, wherein the user mode includes a software interrupt instruction that can be utilized by the fast interrupt handler to request a kernel service;
receiving, by the fast interrupt handler, a fast interrupt request asserted by a hardware device when the operating system is within the kernel critical section, wherein the fast interrupt request includes a request to invoke a kernel service that corresponds to the second priority level interrupt request;
raising, by the fast interrupt handler through the software interrupt instruction when the operating system is within the kernel critical section, the request to invoke the kernel service that corresponds to the second priority level interrupt request;
deferring invocation of the kernel service that corresponds to the second priority level interrupt request to avoid invoking the kernel service that corresponds to the second priority level interrupt request until after the operating system has exited the kernel critical section; and
processing the second priority level interrupt request after the operating system exited the kernel critical section.

14. The method of claim 13 , further including:
after the operating system has exited the kernel critical section continuing to execute the fast interrupt handler in the user mode to service the hardware device.

15. The method of claim 13 , further including:
queuing the requested kernel service that corresponds to the second priority level interrupt request onto a buffer; and
managing the buffer with a lockless increment of reader and writer indices.

16. The method of claim 15 , wherein the fast interrupt handler writes the requested kernel service to the buffer before the operating system exits the kernel critical section and a second priority interrupt handler reads the requested kernel service from the buffer after the operating system exited the kernel critical section.

17. The method of claim 13 , wherein the processor is a component within a reduced instruction set computer (“RISC”) instruction set architecture (“ISA”).

18.

Assignees

• Wind River Systems Inc

Inventors

• Gaiarsa Andrew
• Koning Maarten
• Burton Felix

Classifications

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F13/26 Primary

  with priority control · CPC title