Error correction code management of write-once memory codes

Patent metadata

Field	Value
Publication number	US-9772899-B2
Application number	US-201514703714-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	May 4, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Once Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

First claim

What is claimed is:

1. A circuit, comprising:
a host interface that receives a first data word that includes at least one original symbol having at least two bits;
an error correction code (ECC) controller that encodes the original symbol of the first data word and outputs a first set of ECC bits corresponding to the original symbol of the first data word;
a write-once memory (WOM) controller that encodes the original symbol of the first data word and the first set of ECC bits and outputs a first WOM-encoded word, wherein the first WOM-encoded word includes a first WOM code corresponding to the original symbol of the first data word and a second WOM code corresponding to the first set of ECC bits, wherein the first WOM code includes at least three bits with at least two of the at least three bits having the same logic value; and
a memory device interface that writes the first WOM-encoded word to a first address of a WOM device.

2. The circuit of claim 1 , wherein the memory device interface writes the first WOM-encoded word to the first address by changing a block-initialized state of selected bits of an addressed word of the WOM device, wherein the addressed word is addressed using the first address.

3. The circuit of claim 2 , wherein the block-initialized state is a block-erased state.

4. The circuit of claim 1 , wherein the host interface receives a second data word that includes at least one original symbol having at least two bits;
wherein the ECC controller encodes the original symbol of the second data word and outputs a second set of ECC bits that correspond to the original symbol of the second data word;
wherein the WOM controller encodes the original symbol of the second data word and the second set of ECC bits and outputs a second WOM-encoded word that includes a third WOM code corresponding to the original symbol of the second data word and a fourth WOM code corresponding to the second set of ECC bits, the third WOM code having the same number of bits as the first WOM code;
wherein the memory device interface writes the second WOM-encoded word to the first address of the WOM device; and
wherein, when the original symbol of the second data word differs from the original symbol of the first data word, the third WOM code is equal to the first WOM code with at least two bits inverted and writing the second WOM-encoded word to the first address of the WOM device includes overwriting the first WOM code with the third WOM code.

5. The circuit of claim 4 , wherein, when the original symbol of the second data word and the original symbol of the first data word are the same, the third WOM code and the first WOM code are the same.

6. The circuit of claim 4 , wherein, in response to the host interface receiving a read request for the second data word, the memory device interface reads the second WOM-encoded word from the first address of the WOM device;
wherein the WOM controller decodes the second WOM-encoded word and outputs a first WOM-decoded word including a decoded symbol corresponding to decoding of the third WOM code and a decoded set of ECC bits corresponding to decoding of the fourth WOM code; and
wherein the ECC controller evaluates the decoded symbol and the decoded set of ECC bits to determine whether the decoded symbol matches the original symbol of the second data word and, when the decoded symbol does not match the original symbol of the second data word, takes corrective action to correct the decoded symbol based on the decoded set of ECC bits.

7. The circuit of claim 1 , wherein the ECC controller encodes the original symbol of the first data word in accordance with a Reed-Solomon (RS) encoding scheme.

8. The circuit of claim 1 , wherein the ECC controller encodes the original symbol of the first data word in accordance with a Bose-Chaudhuri-Hocquenghem (BCH) encoding scheme.

9. The circuit of claim 1 , wherein the WOM controller uses a WOM encoding scheme that overwrites once-written WOM-stored data;
wherein the ECC controller uses an ECC encoding scheme that corrects at least one bit error in the WOM-stored data;
wherein the total number of bits of the WOM-stored data does not exceed fifty percent more bits than the number of bits of the original symbol plus the number of bits of the first set of ECC bits; and
wherein the WOM controller outputs three bits for every two bits being encoded.

10. A system comprising:
a host processor that sends a first data word and then sends a second data word, the first data word including a first symbol having at least two bits and the second data word including a second symbol having at least two bits, the first and second symbols having the same number of bits;
a write-once memory (WOM) device communicatively coupled to the host processor;
a host interface that receives data words sent by the host processor;
an error correction code (ECC) controller that encodes symbols in received data words and outputs ECC bits corresponding to the symbols in the received data words;
a WOM controller that encodes the symbols of the received data words and their corresponding ECC bits and outputs corresponding WOM-encoded words; and
a memory device interface that writes the WOM-encoded words to the WOM device;
wherein, when the host interface receives the first data word:
the ECC controller encodes the first symbol and outputs a first set of ECC bits corresponding to the first symbol, the WOM controller encodes the first symbol and the first set of ECC bits and outputs a first WOM-encoded word including a first WOM code corresponding to the first symbol and including at least three bits, and a second WOM code corresponding to the first set of ECC bits, and the memory device interface writes the first WOM-encoded word to a first address of the WOM device;

wherein, when the host interface subsequently receives the second data word:
the ECC controller encodes the second symbol and outputs a second set of ECC bits corresponding to the second symbol, the WOM controller encodes the second symbol and the second set of ECC bits and outputs a second WOM-encoded word including a third WOM code corresponding to the second symbol and having the same number of bits as the first WOM code and a fourth WOM code corresponding to the second set of ECC bits, and the memory device interface writes the second WOM-encoded word to a first address of the WOM device; and

wherein when the second symbol differs from the first symbol:
the third WOM code has at least two bits that differ from the corresponding bits of first WOM code and writing the second WOM-encoded word to the first address of the WOM device includes overwriting the first WOM code with the third WOM code.

11. The system of claim 10 , wherein, when the second symbol and the first symbol are the same, the third WOM code is the same as the first WOM code.

12. The system of claim 10 , wherein, in response to the host interface receiving a read request for the second data word, the memory device interface reads the second WOM-encoded word from the first address of the WOM device, the WOM controller decodes the second WOM-encoded word and outputs a first WOM-decoded word including a decoded symbol corresponding to decoding of the third WOM code and a decoded set of ECC bits corresponding to decoding of the fourth WOM code, and the ECC controller evaluates the decoded symbol and the decoded set of ECC bits to determine whether the decoded symbol matches the second symbol and, when the decoded symbol does not match the second symbol, take corrective action to correct the decoded symbol based on the decoded set of ECC bits.

13. A method comprising:
receiving a

Assignees

• Texas Instruments Inc

Inventors

• Zhang Sai
• Zhu Yuming
• Bittlestone Clive
• Ramaswamy Srinath

Classifications

• G06F11/08 Primary

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title