System and method for isolating I/O execution via compiler and OS support

Patent metadata

Field	Value
Publication number	US-9772879-B2
Application number	US-201615387312-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Feb 19, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An embodiment includes a method includes designating a portion of a plurality of processing cores as an input/output (I/O) core and compiling a program source code to produce compiled program source code, including identifying an I/O operation region of the program source code, determining a number of I/O operations for the I/O operation region, and determining a number of system resources and system resource types for the I/O operation region. The method also includes executing the program source code using the plurality of processing cores, including scheduling the I/O operation region of the program source code on the I/O core of the plurality of processing cores.

First claim

What is claimed is:

1. A method comprising:
designating a portion of a plurality of processing cores as an input/output (I/O) core;
compiling a program source code to produce compiled program source code, comprising:
identifying an I/O operation region and other regions of the program source code;
determining a number of I/O operations for the I/O operation region; and
determining a number of system resources and system resource types for the I/O operation region; and

executing the compiled program source code using the plurality of processing cores, comprising scheduling the I/O operation region of the compiled program source code only on the I/O core of the plurality of processing cores.

2. The method of claim 1 , wherein designating the portion of the plurality of processing cores comprises:
setting interrupt controllers of the plurality of processing cores to ignore I/O interrupts;
selecting the I/O core in response to booting an operating system (OS); and
turning on an interrupt handler for the I/O core in response to loading a driver for an I/O device.

3. The method of claim 2 , wherein turning on the interrupt handler for the I/O core comprises configuring an interrupt request (IRQ) controller to unmask pins on the I/O core, to enable capturing the I/O interrupts by the I/O core.

4. The method of claim 2 , wherein turning on the interrupt handler for the I/O core comprises configuring interrupt-raising memory operations at the I/O device with correct destination addresses.

5. The method of claim 1 , wherein designating at least the portion of the plurality of processing cores comprises selecting a fixed number of cores of the plurality of processing cores or a percentage of core total capacity of the plurality of processing cores as the I/O core.

6. The method of claim 1 , further comprising reselecting the I/O core from the plurality of processing cores dynamically according to a criteria selected from the group consisting of an I/O workload, a system throughput, and other system statistics.

7. The method of claim 1 , wherein compiling the program source code further comprises marking the I/O operation region by inserting, at a start and at an end of the I/O operation region, pragmas annotating the start and the end of the I/O operation region, and wherein executing the program source code comprises translating the pragmas into system calls instructing an operating system (OS) scheduler to move the execution of the I/O operation region to the I/O core.

8. The method of claim 1 , wherein the I/O operation region is identified in accordance with at least one of: sizes of the I/O operation region and other regions of the program source code, a number of I/O requests in the I/O operation region, or estimated execution times of the I/O operation region and the other regions of the program source code.

9. The method of claim 1 , wherein the I/O operation region includes intensive I/O operations in comparison to other regions of the program source code.

10. A method comprising:
compiling a program source code to produce compiled source program code, comprising:
recognizing an input/output (I/O) operation region of the program source code;
determining a number of I/O operations for the I/O operation region;
determining a number of system resources and system resource types for the I/O operation region; and

partitioning the I/O operation region from a non-I/O operation region of the program source code;
executing of the compiled program source code, comprising scheduling the I/O operation region for execution only on a preselected I/O core of a plurality of cores; and
scheduling the non-I/O operation region of the compiled program source code for execution on a non-I/O core of the plurality of cores.

11. The method of claim 10 , wherein recognizing the I/O operation region of the program source code comprises:
calculating a ratio of a number of I/O operations to a number of statements in a piece of the program source code; and
designating the piece of the program source code as the I/O operation region in response to determining that the ratio is above a defined threshold.

12. The method of claim 10 , wherein partitioning the I/O operation region is performed in accordance with a cost model indicating an average runtime costs of I/O operation statements and non-I/O operation statements of the program source code, and wherein partitioning the I/O operation region from the non-I/O operation region of the program source code is performed in accordance with the cost model satisfying load balance between the I/O core and the non-I/O core.

13. The method of claim 10 , wherein compiling the program source code further comprises merging consecutive I/O operation regions of the program source code according to available system resources.

14. The method of claim 10 , wherein compiling the program source code further comprises splitting the I/O operation region and the non-I/O operation region of the program source code according to available system resources.

15. The method of claim 10 , wherein partitioning the I/O operation region from the non-I/O operation region comprises:
inserting pragmas in the I/O operation region, wherein the pragmas mark the I/O operation region; and
inserting, in the I/O operation region, parameters indicating, to a scheduler, a number of I/O operations and a number of estimated runtime cycles.

16. The method of claim 10 , wherein scheduling the I/O operation region for execution on the preselected I/O core comprises creating an I/O operation region scheduler to schedule the I/O operation region.

17. A multiple-core computer comprising:
a plurality of processing cores; and
a non-transitory computer readable storage medium storing programming for execution by at least one processing core of the plurality of processing cores, the programming including instructions to:
designate a portion of a plurality of processing cores as an input/output (I/O) core;
compile a program source code to produce compiled program source code, comprising:
identifying an I/O operation region and other regions of the program source code;
determining a number of I/O operations for the I/O operation region; and
determining a number of system resources and system resource types for the I/O operation region; and

execute the compiled program source code, comprising scheduling the I/O operation region of the compiled program source code only on the I/O core of the plurality of processing cores.

18. The multiple-core computer of claim 17 , wherein the instructions to designate a portion of the plurality of processing cores as the I/O core includes instructions to:
set interrupt controllers of the portion of the plurality of processing cores to ignore I/O interrupts;
select the I/O core in response to booting an operating system (OS); and
turn on an interrupt handler for the I/O core in response to loading a driver for an I/O device.

19. The multiple-core computer of claim 17 , wherein the instructions to identify the I/O operation region of the program source code include instructions to:
insert, at a start and at an end of the I/O operation region, pragmas annotating the start and the end of the I/O operation region; and
insert, in the I/O operation region, parameters indicating, to a subscriber, a number of I/O operations and a number of estimated runtime cycles.

20. The multiple-core computer of claim 17 , wherein the instructions to execute the program source code includes instruc

Assignees

• Futurewei Technologies Inc

Inventors

• Tian Chen
• Ye Handong
• Hu Ziang

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F8/423

  Preprocessors · CPC title

• G06F8/51

  Source to source · CPC title

• G06F8/41

  Compilation · CPC title

• G06F8/451

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title