Solid-state device management

Patent metadata

Field	Value
Publication number	US-9772802-B2
Application number	US-201213619424-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Dec 23, 2011
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.

First claim

What is claimed is:

1. A method comprising:
receiving a write request that includes a first logical address and write data;
establishing, externally to a solid-state storage board by a main board, a correspondence between the first logical address and a first physical address on flash memory devices located on the solid-state storage board, the solid state storage board including an address translation module, the flash memory devices including a plurality of physical memory locations identified by physical addresses, the flash memory devices including a first flash memory device, the solid-state storage board being coupled to the main board via an interface bus, the main board being located on a host computer,
wherein the establishing of the correspondence between the first logical address and the first physical address is responsive to the write request;
providing the correspondence to the solid-state storage board;
storing the correspondence in a location on the solid-state memory devices that is accessible by the address translator module and the solid-state memory devices located on the solid-state storage board;
receiving a status request of the solid-state storage board and determining whether a request to read data is clear to send in response to the status request of the solid-state storage board, wherein the request includes a first logical address; and
facilitating, by the address translator module, a read physical address flash operation from the first flash memory device and providing low latency and high bandwidth delivery of flash commands to the first flash memory device by:
translating the first logical address to the first physical address based on the correspondence, the translating is responsive to the request to read data, and
performing acceleration operations with respect to the translating between logical addresses and physical addresses,
the translating being performed in response to receiving the request to read the data,

wherein the acceleration operations include utilizing an error correction coding of an error correction code decoder and a table to support the translations between logical addresses and physical addresses,
wherein the translating is performed in response to receiving the request to read the data, the request including the first logical address;
retrieving the valid pages within the data from the first physical address,
wherein the establishing of the correspondence between the first logical address and the first physical address is responsive to a projected performance of the main board and characteristics of the first flash memory device to account for a location of prior errors outputted by the error correction code decoder; and
writing the write data in the first flash memory device into a physical location identified by the first physical address,
wherein the acceleration operations include the primary error correction code and redundant array of independent disks acceleration operations to support the writing of the write data and to avoid implementing a second portion of the management complexity by the solid-state storage board,
wherein the acceleration operations includes a garbage collection operation comprising:
finding a best candidate to erase during the garbage collection operation, the best candidate is a block with a least number of valid pages,
queuing a read physical address flash operation for the valid pages within the block, and
queuing physical addresses of the valid pages to be erased, and
queuing a write of the valid pages and logical addresses returned by a physical read.

Assignees

• Franceschini Michele M
• Jagmohan Ashish
• IBM

Inventors

• Franceschini Michele M
• Jagmohan Ashish

Classifications

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0688 Primary

  Non-volatile semiconductor memory arrays · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F3/061

  Improving I/O performance · CPC title