Method for realizing heterogeneous III-V silicon photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-9772447-B2
Application number	US-201615147988-A
Country	US
Kind code	B2
Filing date	May 6, 2016
Priority date	May 7, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A method of producing a heterogeneous photonic integrated circuit includes integrating at least one III-V hybrid device on a source substrate having at least a top silicon layer, and transferring by transfer-printing or by flip-chip bonding the III-V hybrid device and at least part of the top silicon layer of the source substrate to a semiconductor-on-insulator or dielectric-on-insulator host substrate.

First claim

What is claimed is:

1. A method of producing a photonic integrated circuit, the method comprising:
integrating at least one III-V hybrid device on a source substrate having at least a top silicon waveguide layer; and
transferring, by transfer-printing or by flip-chip bonding, the III-V hybrid device and at least part of the top silicon waveguide layer of the source substrate to a semiconductor-on-insulator host substrate.

2. The method of claim 1 , further comprising providing one or more of at least one taper or at least one grating in the top silicon waveguide layer positioned for, in operation, coupling radiation from or to the III-V hybrid device, and wherein transferring at least part of the top silicon waveguide layer comprises transferring the one or more of the at least one taper or the at least one grating.

3. The method of claim 2 , wherein the top silicon waveguide layer of the source substrate includes an adiabatic taper, and the III-V hybrid device comprises a waveguide including a passive taper or an active taper.

4. The method of claim 1 , wherein integrating at least one III-V hybrid device comprises transferring III-V materials to the source substrate, and performing additional processing for forming the hybrid device on the source substrate.

5. The method of claim 4 , wherein transferring III-V materials to the source substrate includes any of multi-wafer bonding or multi-die bonding, adhesive bonding, molecular bonding, flip chip bonding, or transfer printing.

6. The method of claim 1 , wherein the host substrate comprises a host waveguide, and wherein:
the photonic integrated circuit comprises a polymer waveguide configured to couple radiation between the transferred silicon waveguide layer and the host waveguide, or
the photonic integrated circuit comprises a spot converter configured to couple radiation between the transferred silicon waveguide layer and the host waveguide, or
the host substrate and the transferred silicon waveguide layer each comprise diffractive elements aligned to each other and configured perform diffractive assisted coupling of radiation between the transferred silicon waveguide layer and the host waveguide.

7. The method of claim 1 , further comprising obtaining the host substrate, the obtained host substrate being a semiconductor-on-insulator substrate, or a dielectric-on-insulator substrate comprising a waveguide top layer exhibiting a substantial mismatch in effective index with the III-V waveguide mode, thereby allowing the use of standard substrates.

8. The method of claim 1 , further comprising obtaining the host substrate, the obtained host substrate being a dielectric-on-insulator substrate comprising a silicon nitride top layer.

9. The method of claim 1 , wherein integrating a III-V hybrid device comprises integrating any of a laser, amplifier, a modulator, or a detector.

10. A photonic integrated circuit comprising
a host substrate being a semiconductor-on-insulator or dielectric-on-insulator host substrate, and including a host waveguide; and
a III-V hybrid device and silicon layer, the III-V hybrid device being integrated with the silicon layer, and the III-V hybrid device and silicon layer having been transfer-printed or flip-chip bonded on the host substrate together such that, in operation, radiation is coupled between the transferred silicon layer and the host waveguide.

11. The photonic integrated circuit of claim 10 , wherein the silicon layer has been transfer printed, and wherein the silicon layer is positioned between the host substrate and the III-V hybrid device.

12. The photonic integrated circuit of claim 10 , wherein the silicon layer comprises one or more of at least one taper or at least one grating positioned to, in operation, couple radiation from or to the III-V hybrid device.

13. The photonic integrated circuit of claim 10 , wherein the silicon layer comprises an adiabatic taper, and the III-V material forms a waveguide comprising a passive taper or an active taper.

14. The photonic integrated circuit of claim 10 , wherein the host substrate comprises a host waveguide, and wherein:
the photonic integrated circuit comprises a polymer waveguide configured to couple radiation between the transferred silicon layer and the host waveguide; or
the photonic integrated circuit comprises a spot converter configured to couple radiation between the transferred silicon layer and the host waveguide; or
the host substrate and the transferred silicon layer each comprise gratings aligned to each other and configured to perform grating assisted coupling of radiation between the transferred silicon layer and the host waveguide.

15. The photonic integrated circuit of claim 10 , wherein the host substrate comprises a host waveguide being a dielectric-on-insulator wafer comprising a silicon nitride top layer.

Assignees

• Imec Vzw
• Univ Gent

Inventors

• Keyvaninia Shahram
• Van Thourhout Dries
• Roelkens Gunther

Classifications

• G02B2006/12123

  Diode · CPC title

• G02B6/34

  utilising prism or grating {(G02B6/293 takes precedence)} · CPC title

• G02B2006/12121

  Laser · CPC title

• G02B2006/12142

  Modulator · CPC title

• G02B6/12 Primary

  of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title