Beam detector with control circuit

Patent metadata

Field	Value
Publication number	US-9772421-B2
Application number	US-201314406231-A
Country	US
Kind code	B2
Filing date	Apr 15, 2013
Priority date	Jun 14, 2012
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.

First claim

The invention claimed is:

1. A circuit arrangement comprising:
a first capacitor, a second capacitor, and a third capacitor, each of the first capacitor, the second capacitor, and the third capacitor having a first capacitor foil connected to a first circuit node, the first capacitor being supplied with a first time-dependent voltage, the second capacitor being supplied with a second time-dependent voltage, the third capacitor being supplied with a third time-dependent voltage, the first time-dependent voltage and the second time-dependent voltage being clocked in antiphase, the second time-dependent voltage and the third time-dependent voltage being clocked in phase;
an amplifier having inputs connected to the first circuit node and to a ground contact, the amplifier being configured to generate an output signal;
a comparator having two inputs, the comparator being configured to generate an output value; and
a synchronous demodulator configured to apply the output signal of the amplifier synchronously with a clock of the first time-dependent voltage alternately to the two inputs of the comparator,
wherein the circuit arrangement is configured to (i) generate a control value in dependence on the output value of the comparator and (ii) at least one of change amplitudes of the first time-dependent voltage and the third time-dependent voltage in dependence on the control value and change an amplitude of the second time-dependent voltage in dependence on the control value.

2. The circuit arrangement as claimed in claim 1 , further comprising:
a fourth capacitor having a first capacitor foil connected to the first circuit node, the fourth capacitor being supplied with a fourth time-dependent voltage, the first time-dependent voltage and the fourth time-dependent voltage being clocked in phase.

3. The circuit arrangement as claimed in claim 1 , further comprising:
a controllable direct-current source operably connected between the ground contact and a second capacitor foil of one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor;
a resistor operably connected between the second capacitor foil of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor and a second circuit node, the second circuit node having constant voltage potential that is greater than a voltage potential of the ground contact; and
a switch operably connected between the direct-current source and the second capacitor foil.

4. The circuit arrangement as claimed in claim 2 , further comprising:
a first controllable direct-current source having a first contact and a second contact, the second contact being connected to the ground contact;
a first switch operably connected between a second capacitor foil of the first capacitor and the first contact of the first controllable direct-current source;
a first resistor operably connected between the second capacitor foil of the first capacitor and the second current node;
a second controllable direct-current source having a first contact and a second contact, the second contact being connected to the ground contact;
a second switch operably connected between a second capacitor foil of the second capacitor and the first contact of the second controllable direct-current source;
a second resistor operably connected between the second capacitor foil of the second capacitor and the second current node;
a third controllable direct-current source having a first contact and a second contact, the second contact being connected to the ground contact;
a third switch operably connected between a second capacitor foil of the third capacitor and the first contact of the third controllable direct-current source;
a third resistor operably connected between the second capacitor foil of the third capacitor and the second current node;
a fourth controllable direct-current source having a first contact and a second contact, the second contact being connected to the ground contact;
a fourth switch operably connected between a second capacitor foil of the fourth capacitor and the first contact of the fourth controllable direct-current source; and
a fourth resistor operably connected between the second capacitor foil of the fourth capacitor and the second current node.

5. The circuit arrangement as claimed in claim 3 , further comprising:
an inverting amplifier having an inverting input, a non-inverting input, and an output, the inverting input being connected to the second capacitor foil of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor via a first resistor, the non-inverting input being connected to a third circuit node, the third circuit node having a constant voltage potential which is centrally between the voltage potential of the second circuit node and the voltage potential of the ground contact, the output being connected to the inverting input via a second resistor and to a second capacitor foil of another of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor.

6. The circuit arrangement as claimed in claim 1 , further comprising:
a controllable direct-voltage source operably connected between the ground contact and a second capacitor foil of one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and
a second switch operably connected between the direct-voltage source and the second capacitor foil of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the second switch being configured to connect the second capacitor foil of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor either to the controllable direct-voltage source or to the ground contact.

7. The circuit arrangement as claimed in claim 1 , further comprising:
a clock generator configured to (i) generate a clock signal and a push-pull signal that is inverse to the clock signal, (ii) drive the synchronous demodulator with the clock signal, (iii) clock the first time-dependent voltage with the clock signal, and (iv) clock the second time-dependent voltage with the push-pull signal.

8. The circuit arrangement as claimed in claim 1 , further comprising:
a controllable alternating-current source operably connected between the ground contact and a second capacitor foil of one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and
a resistor operably connected between the second capacitor foil of the one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor and a second circuit node, the second circuit node having constant voltage potential that is greater than a voltage potential of the ground contact.

9. The circuit arrangement as claimed in claim 1 , wherein the comparator is one of an integrating comparator and a sample-and-hold comparator.

10. A beam detector comprising:
a circuit arrangement, the circuit arrangement comprising:
a first capacitor, a second capacitor, and a third capacitor, each of the first capacitor, the second capacitor, and the third capacitor having a first capacitor foil connected to a first circuit node, the first capacitor being supplied with a first time-dependent voltage, the second capacitor being supplied with a second time-dependent voltage, the third capacitor being supplied with a third time-dependent voltage, the first time-dependent voltage and the second time-dependent voltage being clocked in antiphase, the second time-dependent voltage and the third time-dependent voltage being clocked in phase;
an amplifi

Assignees

• Bosch Gmbh Robert

Inventors

• Albrecht Andrej
• Zibold Tobias

Classifications

• G01R17/00

  Measuring arrangements involving comparison with a reference value, e.g. bridge · CPC title

• H03K17/00 Primary

  Electronic switching or gating, i.e. not by contact-making and –breaking (gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52) · CPC title

• H03K5/02

  by amplifying (H03K5/04 takes precedence) · CPC title

• G01V3/02 Primary

  operating with propagation of electric current · CPC title