Digital-to-time converter spur reduction

Patent metadata

Field	Value
Publication number	US-9768809-B2
Application number	US-201414318829-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

First claim

What is claimed is:

1. A digital-to-time converter configured to receive a local oscillator signal having a first frequency and to provide an output signal having a second frequency different from the first frequency, the DTC comprising:
one or more delay stages for providing the output signal;
an input coupled to a first delay stage of the one or more delay stages, the input configured to receive the local oscillator signal;
selection logic configured to receive a first code at a first instant, the first code representative of a frequency ramp for providing a first DTC delay, to provide a first delay setpoint to each of the one or more delay stages, to receive the first code at a second instant, and to provide a second delay setpoint to the one or more delay stages; and
wherein the selection logic is configured to select components of at least one of the one or more delay stages differently using the first delay setpoint and the second delay setpoint to provide the first DTC delay.

2. The DTC of claim 1 , wherein the first delay setpoint and the second delay setpoint provide the first DTC delay.

3. The DTC of claim 1 , wherein one stage of the one or more stages includes a first delay path and a second delay path;
wherein the second delay path is a representative of the first delay path; and
wherein the first delay setpoint is configured to select the first delay path at the first instant to provide the first DTC delay, and wherein the second delay setpoint is configured to select the second delay path at the second instant to provide the first DTC delay.

4. The DTC of claim 3 , wherein the first delay path includes a first delay element of the one stage of the one or more delay stages, and wherein the second delay path includes a second delay element of the one of the one or more delay stages.

5. The DTC of claim 4 , wherein the first delay element includes a first multiplexer and the second delay element includes a second multiplexer.

6. The DTC of claim 5 , wherein a control node of the first multiplexer is coupled to a first output of the selection logic; and
wherein a control node of the second multiplexer is coupled to a second output of the selection logic.

7. The DTC of claim 1 , wherein the one or more delay stages includes a first delay stage and a second delay stage;
wherein the first delay setpoint is configured to provide a first delay of the first delay stage and a first delay of the second delay stage;
wherein the second delay setpoint is configured to provide a second delay of the first stage; and
wherein the first delay of the first delay stage is different from the second delay of the first delay stage.

8. The DTC of claim 7 , wherein the first delay stage includes a divider stage; and
wherein the second delay stage includes a plurality of delay elements.

9. The DTC of claim 7 , wherein the first delay stage includes a plurality of delay elements and the second delay stage includes an interpolator.

10. A radio circuit comprising:
a single local oscillator for generating a plurality of carrier signals, the plurality of carrier signals including a plurality of distinct frequencies, the single local oscillator configured to provide a single reference frequency signal;
a plurality of digital-to-time converters (DTCs), each DTC of the plurality of DTCs configured to receive the single reference frequency signal and to provide a carrier signal of the plurality of carrier frequency signals;
wherein each DTC includes:
one or more delay stages for providing the carrier signal;

selection logic configured to receive a first code at a first instant, the first code representative of a frequency ramp for providing a first DTC delay, to provide a first delay setpoint to each of the one or more delay stages, to receive the first code at a second instant, and to provide a second delay setpoint to the one or more delay stages, wherein the first delay setpoint and the second delay setpoint provide the first DTC delay; and
wherein the selection logic is configured to select components of at least one of the one or more delay stages differently using the first delay setpoint and the second delay setpoint to provide the first DTC delay.

11. The DTC of claim 1 , wherein the first delay setpoint and the second delay setpoint provide the first DTC delay.

12. The radio circuit of claim 10 , wherein one of the delay stages of the one or more delay stages includes a first delay path and a second delay path;
wherein the second delay path is a representative of the first delay path; and
wherein the first delay setpoint is configured to select the first delay path at the first instant to provide the first DTC delay, and wherein the second delay setpoint is configured to select the second delay path at the second instant to provide the first DTC delay.

13. The radio circuit of claim 12 , wherein the first delay path includes a first delay element of one of one of the one or more delay stages, and wherein the second delay path includes a second delay element of the one of the one or more delay stages.

14. The radio circuit of claim 10 , wherein the one or more delay stages includes a first delay stage and a second delay stage;
wherein the first delay setpoint is configured to provide a first delay of the first delay stage and a first delay of the second delay stage;
wherein the second delay setpoint is configured to provide a second delay of the first stage; and
wherein the first delay of the first delay stage is different from the second delay of the first delay stage.

15. The radio circuit of claim 14 , wherein the first delay stage includes a divider stage; and
wherein the second delay stage includes a plurality of delay elements.

Assignees

• Intel Ip Corp

Inventors

• Tertinek Stefan
• Preyler Peter
• Mayer Thomas

Classifications

• H04B1/0082 Primary

  with a common local oscillator for more than one band · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title