Receiver for simultaneous signals in carrier aggregation

Patent metadata

Field	Value
Publication number	US-9768797-B2
Application number	US-201514931665-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Mar 12, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described.

First claim

What is claimed:

1. An apparatus comprising:
an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and
a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal, wherein the at least one variable capacitor comprises a loop filter capacitor coupled to an output of an operational transconductance amplifier and coupled to an integration capacitor.

2. The apparatus of claim 1 , wherein the resonator stage circuitry includes at least one additional integration stage including the at least one variable capacitor.

3. The apparatus of claim 1 , wherein the at least one variable capacitor varies the notch frequencies by at least moving zeroes of a second order and/or higher order loop filter of the resonator stage circuitry.

4. The apparatus of claim 1 , wherein the at least one variable capacitor comprises at least one of a first integration capacitor, a second integration capacitor, a third integration capacitor, or a sampling capacitor.

5. The apparatus of claim 4 , the apparatus further comprising:
a mixer stage to downsample a signal received from the radio frequency input port, wherein the mixer stage further includes the first integration capacitor, and wherein the first integration capacitor is further coupled to a transfer capacitance stage circuitry.

6. The apparatus of claim 4 , wherein the resonator stage circuitry includes the second integration capacitor coupled on a first side to the transfer capacitance stage circuitry and on a second side to an input of an operational transconductance amplifier.

7. The apparatus of claim 6 , wherein the resonator stage circuitry includes the loop filter capacitor coupled to the output of the operational transconductance amplifier, and wherein the second integration capacitor comprises the integration capacitor.

8. The apparatus of claim 6 , wherein the resonator stage circuitry includes the third integration capacitor coupled to an output of the operational transconductance amplifier and a quantizer input.

9. The apparatus of claim 6 , wherein the resonator stage circuitry includes the sampling capacitor coupled to the input of the operational transconductance amplifier, and wherein the sampling capacitor is further coupled to an output of the operational transconductance amplifier.

10. The apparatus of claim 1 further comprising:
at least one decimator coupled to the in-phase sigma delta receiver and the quadrature phase sigma delta receiver.

11. The apparatus of claim 1 further comprising:
signal cancellation circuitry to remove at least one unwanted signal from an output signal generated by the in-phase sigma delta receiver and the quadrature phase sigma delta receiver.

12. The apparatus of claim 11 , wherein the signal cancelation circuitry comprises a 90 degree phase shifter, delay circuitry, and at least one combiner.

13. The apparatus of claim 1 , wherein the apparatus is included in a user equipment.

14. The apparatus of claim 1 , wherein the radio frequency input port is configured to receive at least a down converted signal at an intermediate frequency.

15. A method comprising:
receiving, at a first radio frequency input port of an in-phase sigma delta receiver, a signal comprising a first carrier aggregation signal and a second carrier aggregation signal; and
receiving, at a second radio frequency input port of a quadrature phase sigma delta receiver, the signal comprising the first carrier aggregation signal and the second carrier aggregation, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal, wherein the at least one variable capacitor comprises a loop filter capacitor coupled to an output of an operational transconductance amplifier and coupled to an integration capacitor.

16. The method of claim 15 , wherein the resonator stage circuitry includes at least one additional integration stage including the at least one variable capacitor.

17. The method of claim 15 , wherein the at least one variable capacitor varies the notch frequencies by at least moving zeroes of a second order and/or higher order loop filter of the resonator stage circuitry.

18. The method of claim 15 , wherein the at least one variable capacitor comprises at least one of a first integration capacitor, a second integration capacitor, a third integration capacitor, or a sampling capacitor.

19. The method of claim 18 further comprising:
downsampling, at a mixer stage, the received signal, wherein the mixer stage further includes the first integration capacitor, and wherein the first integration capacitor is further coupled to a transfer capacitance stage circuitry.

20. The method of claim 18 , wherein the resonator stage circuitry includes the second integration capacitor coupled on a first side to a transfer capacitance stage circuitry and on a second side to an input of an operational transconductance amplifier.

Assignees

• Nokia Technologies Oy

Inventors

• Jabbour Chadi
• Homayouni Seyed Majid
• Aggarwal Sudhir
• Srini Vason P

Classifications

• H04L5/001

  the frequencies being arranged in component carriers · CPC title

• H03M3/406 Primary

  by the use of a pair of integrators forming a closed loop · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03H19/002

  N-path filters · CPC title