Phase-locked loop with lower power charge pump

Patent metadata

Field	Value
Publication number	US-9768788-B2
Application number	US-201615194533-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Nov 8, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

First claim

What is claimed is:

1. A phase-locked loop comprising:
a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison,
a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, wherein the bias enable signal is de-asserted in response to the phase frequency detector completing a phase frequency detector operation and producing a reset signal,
a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and
a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

2. The phase-locked loop of claim 1 , wherein the reset signal is a delayed phase frequency detector reset signal.

3. The phase-locked loop of claim 1 , wherein the bias enable signal is asserted in response to a falling edge of the reference clock.

4. The phase-locked loop of claim 1 , wherein the phase frequency detector comprises:
a first sequential unit to receive the reference clock;
a second sequential unit to receive the feedback clock;
a logic unit to receive outputs of the first and second sequential units and to generate an output; and
a third sequential unit with a reset or clear input and a clock input, the reset or clear input to receive the reference clock and the clock input to receive the output of the logic unit.

5. The phase-locked loop of claim 4 , wherein the first sequential unit to generate an Up output signal for the charge pump, wherein the second sequential unit to generate a Down output signal for the charge pump, and wherein the bias enable signal is de-asserted after pulse transition in the Up and Down signals completes.

6. The phase-locked loop of claim 1 , wherein the bias generator is disabled for at least 40% of time.

7. A phase-locked loop comprising:
a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse indicating whether the feedback clock needs to be sped up or slowed down relative to the reference clock,
a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, wherein the bias enable signal is de-asserted in response to the phase frequency detector completing a phase frequency detector operation and producing a reset signal,
a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and
a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

8. The phase-locked loop of claim 7 , wherein the reset signal is a delayed phase frequency detector reset signal.

9. The phase-locked loop of claim 7 , wherein the bias enable signal is asserted in response to a falling edge of the reference clock.

10. The phase-locked loop of claim 7 , wherein the phase frequency detector comprises:
a first sequential unit to receive the reference clock;
a second sequential unit to receive the feedback clock;
a logic unit to receive outputs of the first and second sequential units and to generate an output; and
a third sequential unit with a reset or clear input and a clock input, the reset or clear input to receive the reference clock and the clock input to receive the output of the logic unit.

11. The phase-locked loop of claim 10 , wherein the first sequential unit to generate an Up output signal for the charge pump, wherein the second sequential unit to generate a Down output signal for the charge pump, and wherein the bias enable signal is de-asserted after pulse transition in the Up and Down signals completes.

12. The phase-locked loop of claim 7 , wherein the bias generator is disabled for at least 40% of time.

Assignees

• Intel Corp

Inventors

• Goltman Gennady
• Fan Yongping
• Shen Kuan-Yueh

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title