Voltage comparator circuit and method

Patent metadata

Field	Value
Publication number	US-9768761-B2
Application number	US-201615154245-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	May 14, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

This document discusses, among other things, a voltage comparator, an integrated circuit, or a voltage comparison method having increased precision. The hysteresis comparator or the integrated circuit can include first and second input transistors, each having a gate configured to receive a respective first or second input voltage. A bias power source can generate a bias current to a first node by applying a voltage through a first resistor. The first node can be connected to a source of the first input transistor through a second resistor and to a source of the second input transistor through a third resistor. The first, second, and third resistors can include the same type of resistor, with the second and third resistors having different resistance values.

First claim

What is claimed is:

1. A comparator circuit, comprising:
a first input transistor including a gate configured to receive a first input voltage;
a second input transistor including a gate configured to receive a second input voltage;
a first node configured to receive a bias current using a first resistor, the first node coupled to a source of the first input transistor through a second resistor and coupled to a source of the second input transistor through a third resistor;
a comparison output circuit configured to receive a drain voltage from a drain of the first input transistor and to receive a drain voltage from a drain of the second input transistor, and to provide an output signal indicating that the drain voltage of the first input transistor is greater than or less than the drain voltage of the second input transistor; and
a hysteresis comparator including the first and second input transistors, the first, second, and third resistors, and the comparison output circuit,
wherein the first resistor, the second resistor and the third resistor are the same type of resistor, and the second resistor and the third resistor have different resistance values.

2. The comparator circuit of claim 1 , including:
a bias power source configured to apply a voltage to the first resistor to provide the bias current to the first node.

3. The comparator circuit of claim 1 , including:
a reference voltage source configured to apply a voltage to the first resistor to form a first current; and
a current mirror configured to mirror the first current to provide the bias current.

4. The comparator circuit of claim 3 , wherein the reference voltage source is a band-gap voltage source, and wherein the voltage is a band-gap voltage.

5. The comparator circuit of claim 1 , wherein the first resistor includes m 1 fourth resistors having a first resistance value, where m 1 is a positive integer,
wherein the second resistor includes m 2 fourth resistors having the first resistance value, wherein m 2 is a positive integer,
wherein the third resistor includes m 3 fourth resistors having the first resistance value, wherein m 3 is a positive integer, and
wherein m 2 is greater than m 3 .

6. The comparator circuit of claim 1 , including:
a selection circuit configured to select resistance values of the second resistor and the third resistor.

7. The comparator circuit of claim 6 , including:
a resistor string including multiple resistors connected end to end,
wherein a first end of the resistor string is connected to the source of the first input transistor, and a second end of the resistor string is connected to the source of the second input transistor, and
wherein the selection circuit comprises multiple selection paths connected between different resistors of the resistor string, and is configured to select one of the selection paths of a selection input, so as to implement selection of the resistance values of the second resistor and the third resistor.

8. The comparator circuit of claim 1 , wherein the comparison output circuit is configured to provide the output signal to an output terminal.

9. The comparator circuit of claim 1 , including an integrated circuit including the first and second input transistors, the first, second, and third resistors, and the comparison output circuit.

10. A voltage comparison method comprising:
receiving a first input voltage at a gate of a first input transistor;
receiving a second input voltage at a gate of a second input transistor;
receiving a bias current at a first node using a first resistor, the first node coupled to a source of the first input transistor through a second resistor and coupled to a source of the second input transistor through a third resistor;
receiving a drain voltage from a drain of the first input transistor at a comparison output circuit;
receiving a drain voltage from a drain of the second input transistor at the comparison output circuit;
providing, using the comparison output circuit, an output signal indicating that the drain voltage of the first input transistor is greater than or less than the drain voltage of the second input transistor; and
selecting resistance values of the second and third resistors using a selection circuit,
wherein the first resistor, the second resistor and the third resistor are the same type of resistor, and the second resistor and the third resistor have different resistance values.

11. The voltage comparison method of claim 10 , wherein receiving the bias current includes receiving a voltage from a bias power source through the first resistor.

12. The voltage comparison method of claim 10 , including:
receiving a voltage at the first resistor to form a first current;
mirroring the first current using a current mirror to provide the bias current.

13. The voltage comparison method of claim 12 , wherein receiving the voltage includes receiving a band-gap voltage from a band-gap voltage source.

14. The voltage comparison method of claim 10 , wherein the first resistor includes m 1 fourth resistors having a first resistance value, where m 1 is a positive integer,
wherein the second resistor includes m 2 fourth resistors having the first resistance value, wherein m 2 is a positive integer,
wherein the third resistor includes m 3 fourth resistors having the first resistance value, wherein m 3 is a positive integer, and
wherein m 2 is greater than m 3 .

15. The voltage comparison method of claim 10 , wherein selecting resistance values of the second and third resistors using the selection circuit includes selecting one of multiple selection paths between a string of multiple resistors connected between the source of the first input transistor and the source of the second input transistor.

16. The voltage comparison method of claim 10 , wherein providing the output signal includes to an output terminal.

17. A system comprising:
a first input transistor including a gate configured to receive a first input voltage;
a second input transistor including a gate configured to receive a second input voltage;
a first node configured to receive a bias current using a first resistor, the first node coupled to a source of the first input transistor through a second resistor and coupled to a source of the second input transistor through a third resistor;
means for providing an output signal indicating that a drain voltage of the first input transistor is greater than or less than the drain voltage of the second input transistor; and
means for selecting resistance values of the second and third resistors,
wherein the first resistor, the second resistor and the third resistor are the same type of resistor, and the second resistor and the third resistor have different resistance values.

18. The system of claim 17 , wherein the type of resistor comprises one of a well resistor, a poly resistor, a p+ resistor, or an n+ resistor.

19. The system of claim 17 , further comprising a current mirror configured to provide the bias current.

20. The system of claim 17 , wherein the means for selecting comprises means for selecting multiple selection paths coupled between different resistors of a resistor string, wherein the second and third resistors are part of the resistor string.

Assignees

• Fairchild Semiconductor

Inventors

• Huang Lei
• Zhou Jianing
• Li Zhaohong

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title