Differential charge pump with extended output control voltage range

Patent metadata

Field	Value
Publication number	US-9768684-B1
Application number	US-201615334958-A
Country	US
Kind code	B1
Filing date	Oct 26, 2016
Priority date	Oct 26, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

One aspect of the present disclosure relates to a method for operating a charge pump. The method includes comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, and adjusting a gate bias voltage of the current sink transistor and the current reference transistor in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor. The method also includes comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

First claim

The invention claimed is:

1. A system, comprising:
a first feedback circuit configured to compare a drain voltage of a current sink transistor of a charge pump with a drain voltage of a current reference transistor, and to adjust a gate bias voltage of the current sink transistor and the current reference transistor in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor; and
a second feedback circuit configured to compare a common-mode voltage of a loop filter with a reference voltage, and to adjust a gate bias voltage of a current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

2. The system of claim 1 , wherein a first feedback loop of the first feedback circuit has a higher gain and a wider bandwidth than a second feedback loop of the second feedback circuit.

3. The system of claim 1 , wherein the first feedback circuit comprises a first error amplifier having a first input coupled to a drain of the current sink transistor, a second input coupled to a drain of the current reference transistor, and an output coupled to a gate of the current sink transistor and a gate of the current reference transistor.

4. The system of claim 3 , wherein the second feedback circuit comprises a second error amplifier having a first input coupled to the common-mode voltage of the loop filter, a second input coupled to the reference voltage, and an output coupled to a gate of the current source transistor.

5. The system of claim 4 , wherein the first error amplifier has a higher gain than the second error amplifier.

6. The system of claim 4 , wherein the current source transistor comprises an n-type field effect transistor (NFET).

7. The system of claim 1 , wherein the current source transistor sources current to a loop filter and the current sink transistor sinks current from the loop filter.

8. A system, comprising:
a first error amplifier having a first input, a second input coupled to a drain of a current reference transistor, and an output coupled to a gate of the current reference transistor, a gate of a first current sink transistor of a charge pump, and a gate of a second current sink transistor of the charge pump;
a first transmission gate coupled between a drain of the first current sink transistor and the first input of the first error amplifier;
a second transmission gate coupled between a drain of the second current sink transistor and the first input of the first error amplifier; and
a control circuit configured to sense a polarity of a voltage across a loop filter, to turn on the first transmission gate if the sensed polarity of the voltage is positive, and to turn on the second transmission gate if the sensed polarity of the voltage is negative.

9. The system of claim 8 , wherein the first current sink transistor sinks current from a first terminal of the loop filter when the charge pump receives an up signal, and the second current sink transistor sinks current from a second terminal of the loop filter when the charge pump receives a down signal.

10. The system of claim 8 , further comprising a common-mode feedback circuit configured to compare a common-mode voltage of the loop filter with a reference voltage, and to adjust a gate bias voltage of a first current source transistor and a second current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

11. The system of claim 10 , wherein the common-mode feedback circuit comprises a second error amplifier having a first input coupled to the common-mode voltage of the loop filter, a second input coupled to the reference voltage, and an output coupled to a gate of the first current source transistor and a gate of the second current source transistor.

12. The system of claim 11 , wherein the first error amplifier has a higher gain than the second error amplifier.

13. The system of claim 10 , wherein the first current source transistor sources current to a first terminal of the loop filter when the charge pump receives an up signal, and the second current source transistor sources current to a second terminal of the loop filter when the charge pump receives a down signal.

14. The system of claim 13 , wherein the first current sink transistor sinks current from the second terminal of the loop filter when the charge pump receives the up signal, and the second current sink transistor sinks current from the first terminal of the loop filter when the charge pump receives the down signal.

15. The system of claim 10 , wherein the first current source transistor comprises a first n-type field effect transistor (NFET) and the second current source transistor comprises a second NFET.

16. A method for operating a charge pump, comprising:
comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor;
adjusting a gate bias voltage of the current sink transistor and the current reference transistor in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor;
comparing a common-mode voltage of a loop filter with a reference voltage; and
adjusting a gate bias voltage of a current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

17. The method of claim 16 , wherein adjusting the gate bias voltage of the current sink transistor comprises adjusting the gate bias voltage of the current sink transistor using a first error amplifier.

18. The method of claim 17 , wherein adjusting the gate bias voltage of the current source transistor comprises adjusting the gate bias voltage of the current source transistor using a second error amplifier.

19. The method of claim 18 , wherein the first error amplifier has a higher gain than the second error amplifier.

20. The method of claim 16 , wherein the current source transistor comprises an n-type field effect transistor (NFET).

Assignees

• Qualcomm Inc

Inventors

• Banerjee Anirban
• Rasmus Todd Morgan

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0896

  the current generators being controlled by differential up-down pulses · CPC title