System and method for a multi-phase snubber circuit

Patent metadata

Field	Value
Publication number	US-9768607-B2
Application number	US-201514709095-A
Country	US
Kind code	B2
Filing date	May 11, 2015
Priority date	May 11, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

In accordance with an embodiment, a circuit includes a snubber circuit configured to be coupled to outputs of n half-bridge driver circuits that are coupled to n corresponding inductive loads, such that n is an integer greater than one. The snubber circuit includes n diodes and n capacitors. Each of the n diodes are coupled between a corresponding output of the n half-bridge driver circuits and a floating common node, and each of the n capacitors coupled between a corresponding output of the n half-bridge driver circuits and the floating common node.

First claim

What is claimed is:

1. A circuit comprising:
a snubber circuit configured to be coupled to outputs of n half-bridge driver circuits that are coupled to n corresponding inductive loads, wherein n is an integer greater than one, the snubber circuit comprising
n diodes, each of the n diodes coupled between a corresponding output of the n half-bridge driver circuits and a floating common node, and
n capacitors, each of the n capacitors coupled between the corresponding output of the n half-bridge driver circuits and the floating common node; and

n transistors having a first load path terminal coupled to the corresponding output of the n half-bridge driver circuits and a second load path terminal coupled to a corresponding load of the n inductive loads, wherein each of the n diodes is coupled between the first load path terminal of a corresponding transistor of the n transistors and the floating common node, and each of the n capacitors is coupled between the second load path terminal of the corresponding transistor of the n transistors and the floating common node.

2. The circuit of claim 1 , wherein:
n=3; and
the n corresponding inductive loads comprise terminals of a three-phase motor.

3. The circuit of claim 2 , further comprising the n half-bridge driver circuits.

4. The circuit of claim 3 , further comprising the three-phase motor.

5. The circuit of claim 1 , wherein a cathode of each of the n diodes is coupled to the corresponding output of the n half-bridge driver circuits and an anode of each of the n diodes is coupled to the floating common node.

6. The circuit of claim 1 , wherein an anode of each of the n diodes is coupled to the corresponding output of the n half-bridge driver circuits and a cathode of each of the n diodes is coupled to the floating common node.

7. The circuit of claim 1 , further comprising a choke inductor coupled between an output of the n half-bridge driver circuits and a corresponding inductive load of the n corresponding inductive loads.

8. The circuit of claim 1 , wherein an anode of a body diode of each of the n transistors is coupled to its first load path terminal and a cathode of each of the n diodes is coupled to the first load path terminal of the corresponding transistor of the n transistors.

9. The circuit of claim 1 , wherein a cathode of a body diode of each of the n transistors is coupled to its first load path terminal and an anode of each of the n diodes is coupled to the first load path terminal of the corresponding transistor of the n transistors.

10. The circuit of claim 1 , further comprising n transient voltage suppression (TVS) diodes coupled in parallel with corresponding capacitors of the n capacitors.

11. The circuit of claim 1 , further comprising n varistors coupled in parallel with corresponding capacitors of the n capacitors.

12. The circuit of claim 1 , further comprising n overload protection circuits having an output coupled to a corresponding control input of a corresponding transistor of the n transistors, wherein each overload protection circuit is configured to detect an overload condition in its corresponding transistor and shut down its corresponding transistor via the control input of the corresponding transistor when the overload condition is detected.

13. The circuit of claim 12 , further comprising a bus coupled to each of the n overload protection circuits, wherein the each of the n overload protection circuits are configured to assert a signal on the bus when an overload condition is detected, and each of the n overload protection circuits are configured to shut down its corresponding transistor when an asserted signal generated from another overload protection circuit is detected on the bus.

14. The circuit of claim 12 , wherein the overload condition comprises an overcurrent condition.

15. A three-phase motor driving circuit comprising:
a first half-bridge driving circuit having an output coupled to a first load terminal;
a first phase separation transistor having a first load path terminal coupled to the output of the first half-bridge driving circuit and a second load path terminal coupled to the first load terminal;
a first snubber circuit comprising a first diode coupled between the first load path terminal of the first phase separation transistor and a floating common node, and a second capacitor coupled between the second load path terminal of the first phase separation transistor and the floating common node;
a second half-bridge driving circuit having an output coupled to a second load terminal;
a second phase separation transistor having a first load path terminal coupled to the output of the second half-bridge driving circuit and a second load path terminal coupled to the second load terminal;
a second snubber circuit comprising a second diode coupled between the first load path terminal of the second phase separation transistor and the floating common node, and a second capacitor coupled between the second load path terminal of the second phase separation transistor and the floating common node;
a third half-bridge driving circuit having an output coupled to a third load terminal;
a third phase separation transistor having a first load path terminal coupled to the output of the third half-bridge driving circuit and a second load path terminal coupled to the third load terminal; and
a third snubber circuit comprising a third diode coupled between the first load path terminal of the third phase separation transistor and the floating common node, and a third capacitor coupled between the second load path terminal of the third phase separation transistor and the floating common node, wherein the first load terminal, second load terminal and third load terminal are configured to be coupled to a three-phase motor.

16. The circuit of claim 15 , further comprising:
a first choke inductor coupled between the output of the first half-bridge driving circuit and the first load path terminal of the first phase separation transistor;
a second choke inductor coupled between the output of the second half-bridge driving circuit and the first load path terminal of the second phase separation transistor; and
a third choke inductor coupled between the output of the third half-bridge driving circuit and the first load path terminal of the third phase separation transistor.

17. The circuit of claim 15 , wherein:
a cathode of a body diode of the first phase separation transistor is coupled to the first load path terminal of the first phase separation transistor, and an anode of the first diode is coupled to the first load path terminal of the first phase separation transistor;
a cathode of a body diode of the second phase separation transistor is coupled to the first load path terminal of the second phase separation transistor, and an anode of the second diode is coupled to the first load path terminal of the second phase separation transistor; and
a cathode of a body diode of the third phase separation transistor is coupled to the first load path terminal of the third phase separation transistor, and an anode of the third diode is coupled to the first load path terminal of the third phase separation transistor.

18. The circuit of claim 15 , wherein:
an anode of a body diode of the first phase separation transistor is coupled to the first load path terminal of the first phase separation transistor, and a cathode of the first diode is coupled to the first load path terminal of the first phase separation transistor;
an anode of a body diode of the second phase separation tran

Assignees

• Infineon Technologies Ag

Inventors

• Li Chao

Classifications

• H02H7/0838

  with H-bridge circuit · CPC title

• H02M7/5387

  in a bridge configuration · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02H7/085

  against excessive load {(H02H6/00 takes precedence)} · CPC title

• H02H7/09

  against over-voltage; against reduction of voltage; against phase interruption · CPC title