Non volatile resistive memory cell and its method of making

Patent metadata

Field	Value
Publication number	US-9768379-B2
Application number	US-201614989300-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jan 6, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A resistive non-volatile memory cell including a Metal-Insulation-Metal stack including two electrodes and a multilayer of insulation, placed between the two electrodes, including a thin layer of oxide allowing for a resistive transition and an oxygen vacancy reservoir layer is provided. The stack includes from bottom to top: the bottom electrode including a metal layer, the insulation including a layer of stoichiometric metal oxide and a layer of substoichiometric metal oxide forming the oxygen vacancy reservoir layer, and the top electrode including a layer of metal oxide and a metal layer, such that the oxygen vacancy reservoir layer is inserted between two metal oxide stoichiometric layers.

First claim

The invention claimed is:

1. A resistive non-volatile memory cell comprising a stack, the stack comprising:
a bottom electrode comprising a layer of a first metal (M 1 );
a multilayer insulation disposed on the bottom electrode, the multilayer insulation comprising:
an oxide layer including a second layer of stoichiometric metal oxide (I 2 ) and being configured to allow a resistive transition, the second layer of stoichiometric metal oxide (I 2 ) comprising a second metal (M 2 ), and
an oxygen vacancy reservoir layer including a layer of sub stoichiometric metal oxide (I 2 p ); and

a top electrode disposed on the multilayer insulation, the top electrode comprising a third layer of stoichiometric metal oxide (I 3 ) that comprises a third metal (M 3 ) and a layer of a fourth metal (M 4 ),
wherein the oxygen vacancy reservoir layer is disposed between the second layer of stoichiometric metal oxide (I 2 ) and the third layer of stoichiometric metal oxide (I 3 ), and
wherein a third free formation enthalpy (DG 3 ) of at least a portion of the third layer of stoichiometric metal oxide (I 3 ) by oxidation of the third metal (M 3 ) is greater in absolute value than a second free formation enthalpy (DG 2 ) of at least a portion of the second layer of stoichiometric metal oxide (I 2 ) by oxidation of the second metal (M 2 ).

2. The memory cell according to claim 1 , wherein the bottom electrode further comprises a first layer of stoichiometric metal oxide (I 1 ) above the layer of the first metal (M 1 ), the first layer of stoichiometric metal oxide (I 1 ) comprising the first metal (M 1 ).

3. The memory cell according to claim 2 , wherein a first free formation enthalpy (DG 1 ) of at least a portion of the first layer of stoichiometric metal oxide (I 1 ) by oxidation of the first metal (M 1 ) is greater than or equal, in absolute value, to the third free formation enthalpy (DG 3 ) of at least a portion of the third layer of stoichiometric metal oxide (I 3 ) by oxidation of the third metal (M 3 ).

4. The memory cell according to claim 3 , wherein the layer of the first metal (M 1 ) and the layer of the fourth metal (M 4 ) each comprise at least one metal selected from a non-noble metal other than Pd, Ag, Ir, Pt, and Au.

5. The memory cell according to claim 4 , wherein the at least one metal of the layer of the first metal (M 1 ) and of the layer of the fourth metal (M 4 ) is a pure metal, or a binary metal alloy, or a ternary metal alloy, or an alloy with a nitride base or a carbide base or a silicide base or a conductive metal oxide.

6. The memory cell according to claim 1 , wherein the layer of the first metal (M 1 ) and the layer of the fourth metal (M 4 ) each comprise at least one metal selected from TiN, TaN, TiAlN, and TaAlN.

7. The memory cell according to claim 1 , wherein the bottom electrode and the top electrode are symmetrical in the stack.

8. The memory cell according to claim 2 , wherein the first layer of stoichiometric metal oxide (I 1 ) is TiO 2 , or TiON, or Al 2 O 3 .

9. The memory cell according to claim 1 , wherein the second metal (M 2 ) of the second layer of stoichiometric metal oxide (I 2 ) is chosen from among columns III, IV, and V of the periodic table, or is Al, or Si, or a lanthanide.

10. The memory cell according to claim 9 , wherein the second layer of stoichiometric metal oxide (I 2 ) is chosen from among HfO 2 , ZrO 2 , TiO 2 , Al 2 O 3 , Ta 2 O 5 , Nb 2 O 5 , V 2 O 5 , La 2 O 4 , Gd 2 O 3 , Lu 2 O 3 , HfSiO, HfZrO, and SrTiO 3 (STO).

11. The memory cell according to claim 1 , wherein the second layer of stoichiometric metal oxide (I 2 ) has a thickness from 1 nm to 50 nm.

12. The memory cell according to claim 1 , wherein the third metal (M 3 ) is a pure metal, or a binary metal alloy, or a ternary metal alloy.

13. The memory cell according to claim 12 , wherein the third metal (M 3 ) is chosen from among elements Si, Ti, Zr, Hf, Al, Ta, Nb, V, and from among alloys comprising a mixture of said elements.

14. The memory cell according to claim 1 , wherein the stack comprises from bottom to top: TiN/TiO 2 /Ta 2 O 5 /TaO x /TiO 2 /TiN.

15. A microelectronic device comprising the resistive non-volatile memory cell according to claim 1 .

16. The microelectronic device according to claim 15 , further comprising a cavity in which the resistive non-volatile memory cell is at least partially disposed.

17. The microelectronic device according to claim 16 , wherein the bottom electrode of the resistive non-volatile memory cell is disposed underneath and outside of the cavity.

18. The microelectronic device according to claim 16 , wherein the bottom electrode of the memory cell is disposed in the cavity.

19. The microelectronic device according to claim 15 , further comprising a plurality of interconnection levels and a plurality of connection plugs between the levels, each connection plug comprising a cavity in which the resistive non-volatile memory cell is at least partially disposed.

20. A method for manufacturing a resistive non-volatile memory cell according to claim 1 , the method comprising the following successive steps:
forming the bottom electrode by depositing the layer of the first metal (M 1 );
depositing the second layer of stoichiometric metal oxide (I 2 ),
depositing a layer of the third metal (M 3 );
forming the layer of substoichiometric metal oxide (I 2 p) and the third layer of stoichiometric metal oxide (I 3 ) by reacting the third metal (M 3 ) with the second layer of stoichiometric metal oxide (I 2 ); and
depositing the layer of the fourth metal (M 4 ).

21. The method according to claim 20 , wherein the depositing of the layer of the third metal (M 3 ) is performed by flash vapor phase deposition.

22. The method according to claim 20 , wherein the layer of the third metal (M 3 ) is deposited to a thickness from 0.1 nm to 2 nm.

23. The method according to claim 20 , wherein the second layer of stoichiometric metal oxide (I 2 ) is deposited by chemical deposition.

24. The method according to claim 23 , wherein the second layer of stoichiometric metal oxide (I 2 ) is treated with plasma or by plasma nitriding.

25. The method according to claim 24 , wherein the second layer of stoichiometric metal oxide (I 2 ) is implanted with aluminum.

26. A method for manufacturing a resistive non-volatile memory cell according to claim 16 , the method comprising the following successive steps:
compliant depositing the second layer of stoichiometric metal oxide (I 2 ) in the cavity;
depositing a layer of the third metal (M 3 ) in the cavity;
forming the layer of substoichiometric metal oxide (I 2 p ) and the third layer of stoichiometric metal oxide (I 3 ) by reacting the third metal (M 3 ) with the second layer of stoichiometric metal oxide (I 2 ); and
depositing the layer of the fourth metal (M 4 ) in the cavity.

27. The method according to claim 26 , further comprising, before the depositing of the second layer of stoichiometric metal oxide (I 2 ), forming the bottom electrode by compliant depositing the layer of the first metal (M 1 ) in the cavity.

28. A microelectronic device comprising a resistive non-volatile memory cell and a cavity in which the resistive non-volatile memory cell is at least partially disposed, the resistive non-volatile memory cell comprising a stack, the stack comprising:
a bottom electrod

Assignees

• Commissariat Energie Atomique

Inventors

• Gassilloud Remy
• Bernard Mathieu

Classifications

• H01L45/1608

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/08 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic