Systems and methods for fabrication of superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-9768371-B2
Application number	US-201314383837-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	Mar 8, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

First claim

The invention claimed is:

1. A method of depositing a hybrid dielectric, the method comprising:
depositing a first superconducting metal layer;
depositing a first dielectric layer that directly overlies the first superconducting metal layer, the first dielectric layer comprising a first dielectric material;
depositing a second dielectric layer over at least a portion of the first dielectric layer, the second dielectric layer comprising a second dielectric material; and
depositing a third dielectric layer over at least a portion of the second dielectric layer, the third dielectric layer comprising a third dielectric material; and
depositing a second superconducting metal layer, wherein the second superconducting metal layer directly overlies the third dielectric layer.

2. The method of claim 1 wherein:
depositing a first dielectric layer comprising a first dielectric material includes depositing a first layer of silicon nitride that directly overlies the first superconducting metal layer;
depositing a second dielectric layer comprising a second dielectric material includes depositing a layer of silicon dioxide that directly overlies the first layer of silicon nitride; and
depositing a third dielectric layer comprising a third dielectric material includes depositing a second layer of silicon nitride that directly overlies the layer of silicon dioxide.

3. The method of claim 1 wherein depositing a first dielectric layer that directly overlies the first superconducting metal layer includes depositing a non-oxide dielectric that directly overlies the first superconducting metal layer.

4. The method of claim 3 wherein depositing a second dielectric layer over at least a portion of the first dielectric layer includes depositing an oxide dielectric over at least a portion of the first dielectric layer.

5. The method of claim 1 wherein depositing a second dielectric layer over at least a portion of the first dielectric layer includes depositing an oxide dielectric over at least a portion of the first dielectric layer.

6. The method of claim 1 wherein depositing a third dielectric layer over at least a portion of the second dielectric layer includes depositing a third dielectric layer comprising the first dielectric material.

Assignees

• D Wave Systems Inc

Inventors

• Ladizinsky Eric
• Hilton Jeremy P
• Oh Byong Hyop
• Bunyk Paul I

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H01L39/125

  Electricity · mapped topic