Optoelectronic detectors having a dilute nitride layer on a substrate with a lattice parameter nearly matching GaAs

Patent metadata

Field	Value
Publication number	US-9768339-B2
Application number	US-201615188396-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Jun 22, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×10 16 cm −3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

First claim

What is claimed is:

1. A semiconductor, comprising:
a substrate with a lattice parameter matching or nearly matching GaAs;
a first doped III-V layer over the substrate;
an absorber layer over the first doped III-V layer, the absorber layer having:
a dilute nitride comprising In x Ga 1−x N y As 1−y−z Sb z (0≦x≦1; 0≦y≦0.1; 0<z≦ 0.1667),
an In/Sb ratio of at least approximately 6,
a bandgap between approximately 0.7 eV and 0.95 eV, and
a carrier concentration less than approximately 1×10 16 cm −3 at room temperature; and

a second doped III-V layer over the absorber layer.

2. The semiconductor of claim 1 wherein the dilute nitride comprises In x Ga 1−x N y As 1−y−z Sb z (0≦x≦0.55; 0<y≦0.1; 0<z≦0.1).

3. The semiconductor of claim 1 , wherein the carrier concentration of the absorber layer is less than approximately 5×10 15 cm −3 .

4. The semiconductor of claim 1 , wherein the carrier concentration of the absorber layer is less than approximately 1×10 15 cm −3 .

5. The semiconductor of claim 1 , wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.

6. The semiconductor of claim 1 , wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.

7. The semiconductor of claim 1 , further comprising a multiplication layer between the absorber layer and one of the first and second doped III-V layers.

8. The semiconductor of claim 1 , wherein the substrate comprises GaAs.

9. The semiconductor of claim 1 , wherein the first doped III-V layer is n-type and the second doped III-V layer is p-type.

10. The semiconductor of claim 1 , wherein the first doped III-V layer is p-type and the second doped III-V layer is n-type.

11. The semiconductor of claim 1 , wherein the absorber layer is p-type.

12. The semiconductor of claim 1 , wherein the substrate comprises:
a silicon substrate; and
a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.

13. The semiconductor of claim 12 , wherein the lattice engineered layer comprises a Si x Ge 1−x , layer, with x graded from 1 at a surface of the Si x Ge 1−x , layer nearest the silicon substrate to 0 at a surface of the Si x Ge 1−x , layer opposite the silicon substrate.

14. The semiconductor of claim 12 , wherein the lattice engineered layer comprises a rare earth containing layer, the rare earth containing layer comprising one or more of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and/or Lu.

15. A method of forming a semiconductor, comprising:
forming a first doped III-V layer over a substrate with a lattice parameter matching or nearly matching GaAs;
forming an absorber layer over the first doped III-V layer, the absorber layer having:
a dilute nitride comprising In x Ga 1−x N y As 1−y−z Sb z (0≦x≦1; 0<y≦0.1; 0<≦ 0.1667),
an In/Sb ratio of at least approximately 6,
a bandgap between approximately 0.7 eV and 0.95 eV, and
a carrier concentration less than approximately 1×10 16 cm −3 at room temperature; and

forming a second doped III-V layer over the absorber layer.

16. The method of claim 15 , wherein the dilute nitride comprises In x Ga 1−x N y As 1−y−z Sb z (0≦x≦0.55; 0<y≦0.1; 0<z≦0.1).

17. The method of claim 15 , wherein the carrier concentration of the absorber layer is less than approximately 5×10 15 cm −3 .

18. The method of claim 15 , wherein the carrier concentration of the absorber layer is less than approximately 1×10 15 cm −3 .

19. The method of claim 15 , wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.

20. The method of claim 15 , wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.

21. The method of claim 15 , further comprising forming a multiplication layer between the absorber layer and one of the first and second doped III-V layers.

22. The method of claim 15 , wherein the substrate comprises GaAs.

23. The method of claim 15 , wherein the first doped III-V layer is n-type and the second doped III-V layer is p-type.

24. The method of claim 15 , wherein the first doped III-V layer is p-type and the second doped III-V layer is n-type.

25. The method of claim 15 , wherein the absorber layer is p-type.

26. The method of claim 15 , wherein the substrate comprises:
a silicon substrate; and
a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.

27. The method of claim 26 , wherein the lattice engineered layer comprises a Si x Ge 1−x layer, with x graded from 1 at a surface of the Si x Ge 1−x layer nearest the silicon substrate to 0 at a surface of the Si x Ge 1−x layer opposite the silicon substrate.

28. The method of claim 26 , wherein the lattice engineered layer comprises a rare earth containing layer, the rare earth containing layer comprising one or more of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and/or Lu.

Assignees

• Iqe Plc

Inventors

• Yanka Robert
• Chung Seokjae
• Nunna Kalyan
• Pelzel Rodney
• Williams Howard

Classifications

• H01L31/1848

  Electricity · mapped topic

• H01L31/105

  Electricity · mapped topic

• Y02E10/544

  Solar cells from Group III-V materials · CPC title

• H01L31/1075 Primary

  Electricity · mapped topic

• H01L31/03048

  Electricity · mapped topic