Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in different regions

Patent metadata

Field	Value
Publication number	US-9768330-B2
Application number	US-201414467449-A
Country	US
Kind code	B2
Filing date	Aug 25, 2014
Priority date	Aug 25, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. An integrated structure comprising:
a first photonic device formed of a first polysilicon material;
a second photonic device formed of a second polysilicon material, different from the first polysilicon material, wherein the first polysilicon material and second polysilicon material are coplanar in the integrated structure and have different optical properties, wherein the first and second polysilicon materials reside on a common physical layer of the integrated structure; and
an electronic circuit comprising at least one transistor, wherein a gate of the at least one transistor is formed of the first polysilicon material.

2. An integrated structure as in claim 1 , wherein the first and second polysilicon materials have different optical transmission properties.

3. An integrated structure as in claim 1 , wherein the first and second polysilicon materials have different optical absorption properties.

4. An integrated structure as in claim 1 wherein the first and second polysilicon materials have different grain structures.

5. An integrated structure as in claim 1 , wherein the first photonic device comprises a defect state photodetector and the second photonic device comprises a waveguide.

6. An integrated structure as in claim 5 , wherein the second polysilicon material comprises an amorphized and recrystallized polysilicon material.

7. An integrated structure as in claim 5 , wherein the second polysilicon material is located in a region where the first polysilicon material has been removed.

8. An integrated structure as in claim 5 , further comprising a nitride material over the second polysilicon material, but not over the first polysilicon material.

9. An integrated structure as in claim 8 , wherein the nitride material comprises silicon nitride.

10. An integrated structure as in claim 1 , further comprising a first dielectric isolation region within a substrate for electrically isolating the transistor and a second deeper dielectric optical isolation region within the substrate and below the second polysilicon material.

Assignees

• Micron Technology Inc
• Massachusetts Inst Technology

Inventors

• Meade Roy
• Mehta Karan
• Megged Efraim
• Orcutt Jason
• Popovic Milos
• Ram Rajeev
• Shainline Jeffrey
• Sternberg Zvi
• Stojanovic Vladimir
• Tehar-Zahav Ofer

Classifications

• H01L27/1443

  Electricity · mapped topic

• H01L31/02327 Primary

  Electricity · mapped topic

• H01L31/1804

  Electricity · mapped topic

• H01L31/03682

  Electricity · mapped topic

• H10F77/1642

  including only Group IV materials · CPC title