Thin film transistor, manufacturing method thereof, array substrate, and display device

Patent metadata

Field	Value
Publication number	US-9768312-B2
Application number	US-201514913048-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Apr 3, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.

First claim

The invention claimed is:

1. A manufacturing method of a thin film transistor, comprising a step of forming an active layer, wherein the step of forming an active layer comprises:
forming a first amorphous silicon layer;
performing a first excimer laser annealing, so as to convert the first amorphous silicon layer into a first poly-silicon layer;
forming a second amorphous silicon layer on an upper surface of the first poly-silicon layer, and adding dopant ions in the process of forming the second amorphous silicon layer; and
performing a second excimer laser annealing, so as to melt the upper surface layer of the first poly-silicon layer and cause the second amorphous silicon layer to grow into the molten upper surface of the first poly-silicon layer, thereby forming a second poly-silicon layer, wherein the dopant ions are added into the molten upper surface layer of the first poly-silicon layer.

2. The manufacturing method of a thin film transistor according to claim 1 , further comprising, before forming the first amorphous silicon layer, a step of forming a buffer layer.

3. The manufacturing method of a thin film transistor according to claim 1 , wherein, between forming the first amorphous silicon layer and performing the first excimer laser annealing, the manufacturing method further comprises: performing a first dehydrogenation process; and between forming the second amorphous silicon layer and performing the second excimer laser annealing, the manufacturing method further comprises: performing a second dehydrogenation process.

4. The manufacturing method of a thin film transistor according to claim 1 , further comprising, before forming the second amorphous silicon layer on the upper surface of the first poly-silicon layer, a step of: performing a surface treatment on the first poly-silicon layer;
wherein the surface treatment is performed on the first poly-silicon layer by using hydrofluoric acid HF—ozone water O3—hydrofluoric acid HF—hydrogen water H2.

5. The manufacturing method of a thin film transistor according to claim 1 , wherein in the process of performing the second excimer laser annealing, laser energy is controlled such that thickness of the melt upper surface layer of the first poly-silicon layer is no larger than 10 nm.

6. The manufacturing method of a thin film transistor according to claim 5 , wherein the laser energy is controlled by lowering scanning energy and/or scanning step frequency in the second excimer laser annealing.

7. The manufacturing method of a thin film transistor according to claim 1 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

8. The manufacturing method of a thin film transistor according to claim 2 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

9. The manufacturing method of a thin film transistor according to claim 3 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

10. The manufacturing method of a thin film transistor according to claim 4 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

11. The manufacturing method of a thin film transistor according to claim 5 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

12. The manufacturing method of a thin film transistor according to claim 6 , wherein the first amorphous silicon layer has a thickness in the range of 30 nm to 50 nm; and the second amorphous silicon layer has a thickness in the range of 2 nm to 10 nm.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Tian Hongwei
• Niu Yanan
• Wang Zuqiang
• Sun Liang

Classifications

• H10P95/94

  Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P14/3808

  using laser beams · CPC title