I-shaped gate electrode for improved sub-threshold MOSFET performance

Patent metadata

Field	Value
Publication number	US-9768296-B2
Application number	US-201514846398-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Oct 15, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit comprising at least one metal-oxide semiconductor (MOS) transistor, comprising the steps of:
forming isolation dielectric structures at selected locations of a semiconductor surface of a body, the isolation dielectric structures defining a substantially rectangular active region of a first conductivity type at the surface, the active region having first and second parallel edges extending in a first direction, and third and fourth parallel edges extending in a second direction perpendicular to the first direction;
forming a gate dielectric layer at the surface of the active region;
depositing a gate material over the gate dielectric layer;
removing selected portions of the deposited gate material to define a gate structure overlying a portion of the active region, the gate structure comprising:
a plurality of central portions, each central portion extending over the active region in the second direction; and
first and second end portions at opposite ends of the plurality of central portions, each end portion disposed upon an isolation dielectric structure of the isolation dielectric structures adjacent to the active region, the first and second end portions overlapping the isolation dielectric structure at the first and second edges, respectively, of the active region, wherein the removing step defines the gate structure as a single contiguous structure, so that the first end portion is contiguous with each of the plurality of central portions at one end, and the second end portion is contiguous with each of the plurality of central portions at the other end, and wherein the first and second end portions of the gate structure each also overlap the isolation dielectric structure at the third and fourth edges of the active region; and

doping, to a second conductivity type, locations of the active region on opposite sides of each of the central portions of the gate structure to form source/drain regions.

2. The method of claim 1 , wherein the gate structure comprises one or more materials selected from the group consisting of polycrystalline silicon, a metal, and a conductive metal compound.

3. The method of claim 1 , wherein the step of forming the isolation dielectric structures comprises:
etching recesses into the surface at the selected locations;
depositing a dielectric material overall; and
planarizing the dielectric material to expose the active region and form the isolation dielectric structures as the dielectric material remaining in the recesses.

4. A method of fabricating an integrated circuit comprising at least one metal-oxide semiconductor (MOS) transistor, comprising the steps of:
forming an isolation dielectric structure at a semiconductor surface of a body, the isolation dielectric structure having first and second parallel edges extending in a first direction and third and fourth parallel edges extending in a second direction perpendicular to the first direction;
forming a gate dielectric layer at the surface of the region;
depositing a gate material over the gate dielectric layer;
removing selected portions of the deposited gate material to define a gate structure, the gate structure comprising:
a plurality of central portions, each central portion extending over the semiconductor surface in the second direction; and
first and second end portions at opposite ends of the plurality of central portions, each end portion disposed upon the isolation dielectric structure, the first end portion overlapping the isolation dielectric structure along the entire first edge and the second end portion overlapping the isolation dielectric structure along the entire second edge, wherein the removing step defines the gate structure as a single contiguous structure, so that the first end portion is contiguous with each of the plurality of central portions at one end, and the second end portion is contiguous with each of the plurality of central portions at the other end, and wherein the first and second end portions of the gate structure each also overlap the isolation dielectric structure at the third and fourth parallel edges of the active region; and

doping, to a second conductivity type, locations of the semiconductor surface on opposite sides of each of the central portions of the gate structure to form source/drain regions.

5. The method of claim 4 , wherein the gate structure comprises one or more materials selected from the group consisting of polycrystalline silicon, a metal, and a conductive metal compound.

6. The method of claim 4 , wherein the step of forming the isolation dielectric structures comprises:
etching recesses into the semiconductor surface at the selected location;
depositing a dielectric material overall; and
planarizing the dielectric material to expose the semiconductor surface and form the isolation dielectric structures as the dielectric material remaining in the recesses.

7. The method of claim 4 , wherein the plurality of central portions includes at least three central portions.

8. The method of claim 4 , wherein the body is a single-crystal silicon substrate.

9. The method of claim 4 , wherein the isolation dielectric structure is a shallow trench isolation (STI) structure.

10. The method of claim 4 , wherein the isolation dielectric structure defines an active region and the plurality of central portions extend over the active area.

11. The method of claim 4 , further comprising forming contact openings to the gate structure, wherein all contact openings to the gate structure are formed over the isolation dielectric structure.

12. A method of fabricating an integrated circuit comprising:
forming an isolation dielectric structure at a surface of a substrate, the isolation dielectric structure defining a substantially rectangular active region, the active region having first and second parallel edges extending in a first direction and third and fourth parallel edges extending in a second direction perpendicular to the first direction;
forming a p-well in the substrate;
forming a gate structure overlying the active region, the gate structure comprising:
a plurality of central portions, each central portion extending over the active region in the second direction; and
first and second end portions at opposite ends of the plurality of central portions, the first and second end portions overlapping the isolation dielectric structure at the first and second edges, respectively, of the active region, wherein the gate structure is a single contiguous structure, so that the first end portion is contiguous with each of the plurality of central portions at one end, and the second end portion is contiguous with each of the plurality of central portions at the other end, and wherein the first and second end portions of the gate structure each also overlap the isolation dielectric structure at the third and fourth edges of the active region; and

forming source/drain regions in the p-well on opposite sides of each of the central portions of the gate structure.

13. The method of claim 12 , wherein the gate structure comprises one or more materials selected from the group consisting of polycrystalline silicon, a metal, and a conductive metal compound.

14. The method of claim 12 , wherein forming the isolation dielectric structure comprises:
etching a recess into the semiconductor surface at the selected location;
depositing a dielectric material overall; and
planarizing the dielectric material to expose the semiconductor surface and form the isolation dielectric structure as the dielectric material remaining in the recess.

Assignees

• Texas Instruments Inc

Inventors

• Chatterjee Amitava

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/4238

  Electricity · mapped topic