Switching device

Patent metadata

Field	Value
Publication number	US-9768287-B1
Application number	US-201715425714-A
Country	US
Kind code	B1
Filing date	Feb 6, 2017
Priority date	Mar 9, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including the first trenches. In an interlayer insulating film, a contact hole is provided within the first element range, and a wide contact hole is provided within the inactive range. The first metal layer contacts the semiconductor substrate within the contact hole and the wide contact hole. The insulating protective film covers an outer peripheral side portion of a bottom surface of a second recess which is provided in a surface of the first metal layer above the wide contact hole. A side surface of an opening provided in a portion of the insulating protective film that includes the first element range is disposed in the second recess. The second metal layer contacts the first metal layer and the side surface of the opening.

First claim

What is claimed is:

1. A switching device comprising: a semiconductor substrate; gate insulating films; gate electrodes; an interlayer insulating film; a first metal layer; a second metal layer, and an insulating protective film,
wherein
the semiconductor substrate comprises a first element range and an ineffective range,
a plurality of first trenches is provided in an upper surface of the semiconductor substrate within the first element range and is not provided within the ineffective range, the first trenches extending along a first direction and being arranged at intervals along a second direction perpendicular to the first direction,
the ineffective range is provided adjacent to the first element range in the second direction,
the gate insulating films cover inner surfaces of the first trenches,
the gate electrodes are disposed inside of the first trenches, each gate electrode being insulated from the semiconductor substrate by the corresponding gate insulating film,
the interlayer insulating film covers the upper surface and the gate electrodes,
within the first element range, a contact hole is provided in a portion of the interlayer insulating film that covers the upper surface,
within the ineffective range, a wide contact hole is provided in a portion of the interlayer insulating film that covers the upper surface, the wide contact hole having a width in the second direction that is wider than a pitch between each pair of adjacent first trenches in the second direction,
the first metal layer covers the interlayer insulating film, being insulated from the gate electrodes by the interlayer insulating film, the first metal layer being in contact with the semiconductor substrate within the contact hole and the wide contact hole,
a first recess is provided in a surface of the first metal layer above the contact hole, and a second recess is provided in the surface of the first metal layer above the wide contact hole,
the insulating protective film covers an outer peripheral side part of a bottom surface of the second recess,
an opening is provided in the insulating protective film in a range wider than the first element range and including the first element range, a side surface of the opening being disposed in the second recess,
the second metal layer is in contact with the surface of the first metal layer in the opening and is in contact with the side surface of the opening, the second metal layer having a linear expansion coefficient smaller than a linear expansion coefficient of the first metal layer,
each semiconductor region interposed between each pair of adjacent first trenches in the first element range comprises:
a first region of a first conductivity type, being in contact with the first metal layer in the contact hole, being in contact with the corresponding gate insulating film; and
a body region of a second conductivity type, being in contact with the first metal layer in the contact hole, and being in contact with the corresponding gate insulating film below the first region,

the semiconductor region within the ineffective range comprises a second conductivity type peripheral region of the second conductivity type, the second conductivity type peripheral region being in contact with the first metal layer in the wide contact hole, and extending from the upper surface to a position deeper than lower ends of the first trenches,
the semiconductor substrate further comprises a second region of the first conductivity type, the second region being disposed and extending across below the body region and below the second conductivity type peripheral region, being in contact with the gate insulating films below the body region, and being separated from the first region by the body region.

2. The switching device of claim 1 , wherein a plurality of second trenches is provided in the upper surface, each of the second trenches extending toward the ineffective range from the first trench positioned closest to the ineffective range, and
each end surface of the second trenches on an ineffective range side is covered with the second conductivity type peripheral region.

3. The switching device of claim 1 , wherein a second conductivity-type impurity density of the second conductivity-type peripheral region is higher than a second conductivity-type impurity density of a portion of the body region that is positioned below the first region.

4. The switching device of claim 1 , wherein
the semiconductor substrate includes an outer peripheral voltage resistant range that surrounds a periphery of a range including the first element range and the ineffective range, and
a guard ring of the second conductivity type is provided in the outer peripheral voltage resistant range, the guard ring being exposed on the upper surface, surrounding the range including the first element range and the ineffective range, and being electrically separated from the first metal layer.

5. The switching device of claim 4 , wherein
the semiconductor substrate further includes a second element range arranged between the ineffective range and the outer peripheral voltage resistant range,
a plurality of the first trenches is provided at intervals along the second direction in the upper surface within the second element range,
within the second element range, a contact hole is provided in a portion of the interlayer insulation film that covers the upper surface,
the first metal layer is in contact with the upper surface in the contact hole within the second element range,
the insulating protective film covers the first metal layer within the second element range,
the second metal layer is disposed and extending across from on the first metal layer in the opening and to on the insulating protective film,
an outer peripheral side end of the second metal layer is positioned on an inner peripheral side relative to an outer peripheral side end of the first metal layer, and
each of the semiconductor regions interposed between each pair of adjacent first trenches within the second element range includes the first region and the body region.

Assignees

• Toyota Motor Co Ltd

Inventors

• Soeno Akitaka
• Kuno Takashi

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/387

  Flow barriers · CPC title