Thin film transistor array substrate and organic light-emitting diode display including the same

Patent metadata

Field	Value
Publication number	US-9768240-B2
Application number	US-201514712703-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Oct 6, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A thin film transistor (TFT) array substrate and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the array substrate includes a substrate, a driving TFT formed over the substrate and including a driving gate electrode, and a storage capacitor including a first electrode electrically connected to the driving gate electrode and a second electrode formed over and insulated from the first electrode. The array substrate also includes an interlayer insulating film at least partially covering the first electrode and a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT. The driving voltage line is formed on the same layer as the second electrode.

First claim

What is claimed is:

1. A thin film transistor (TFT) array substrate comprising:
a substrate;
a driving TFT formed over the substrate and comprising a driving gate electrode, source and drain electrodes, and a driving semiconductor layer;
a gate insulating film formed over the substrate to cover the driving semiconductor layer and insulate the driving semiconductor layer from the driving gate electrode;
a storage capacitor comprising a first electrode electrically connected to the driving gate electrode and a second electrode formed over the driving TFT and formed over and insulated from the first electrode, wherein the source and drain electrodes of the driving TFT and the second electrode of the storage capacitor are separate electrodes;
an interlayer insulating film formed over the driving TFT and at least partially covering the first electrode and insulating the first electrode from the second electrode; and
a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT,
wherein the driving voltage line is formed on a same layer as the second electrode.

2. The thin film transistor array substrate of claim 1 , further comprising a first via layer formed over the interlayer insulating film and having first and second opening portions exposing portions of an upper surface of the interlayer insulating film.

3. The thin film transistor array substrate of claim 2 , wherein the second electrode is formed in the first opening portion on the upper surface of the interlayer insulating film.

4. The thin film transistor array substrate of claim 1 , further comprising a switching TFT formed over the substrate and comprising source and drain electrodes formed of a same material as the second electrode.

5. The thin film transistor array substrate of claim 1 , wherein the interlayer insulating film is formed of an organic material.

6. The thin film transistor array substrate of claim 1 , wherein the driving gate electrode and the first electrode are formed as one body over a layer.

7. A thin film transistor (TFT) array substrate comprising:
a substrate;
a driving TFT formed over the substrate and comprising a driving gate electrode;
a storage capacitor comprising a first electrode electrically connected to the driving gate electrode and a second electrode formed over and insulated from the first electrode;
an interlayer insulating film at least partially covering the first electrode; and
a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT,
wherein the driving voltage line is formed on a same layer as the second electrode;
a first via layer formed over the interlayer insulating film and having first and second opening portions exposing portions of an upper surface of the interlayer insulating film,
wherein the driving voltage line is formed in the second opening portion on the upper surface of the interlayer insulating film.

8. A thin film transistor (TFT) array substrate comprising:
a substrate;
a driving TFT formed over the substrate and comprising a driving gate electrode, source and drain electrodes, and a driving semiconductor layer;
a gate insulating film formed over the substrate to cover the driving semiconductor layer and insulate the driving semiconductor layer from the driving gate electrode;
a storage capacitor comprising a first electrode electrically connected to the driving gate electrode and a second electrode formed over the driving TFT and formed over and insulated from the first electrode;
an interlayer insulating film formed over the driving TFT and at least partially covering the first electrode and insulating the first electrode from the second electrode;
a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT,
wherein the driving voltage line is formed on a same layer as the second electrode,
a first via layer formed over the interlayer insulating film and having first and second opening portions exposing portions of an upper surface of the interlayer insulating film;
a second via layer formed over an upper portion of the first via layer and having a first via hole and a second via hole; and
a bridge formed over an upper portion of the second via layer and configured to electrically connect the second electrode to the driving voltage line.

9. A thin film transistor (TFT) array substrate comprising:
a substrate;
a driving TFT and a switching TFT formed over the substrate, wherein the driving TFT comprises a driving gate electrode, and wherein the switching TFT comprises a gate, source and drain electrodes;
a storage capacitor comprising a first electrode electrically connected to the driving gate electrode and a second electrode formed over and insulated from the first electrode;
an interlayer insulating film at least partially covering the first electrode and the gate electrode of the switching TFT; and
a first via layer formed over an upper surface of the interlayer insulating film and having first and second opening portions exposing portions of the upper surface of the interlayer insulating film,
wherein the second electrode is formed in the first opening portion on the upper surface of the interlayer insulating film and is formed of a same material as the source and drain electrodes of the switching TFT.

10. The thin film transistor array substrate of claim 9 , further comprising a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT, wherein the driving voltage line is formed in the second opening portion on the upper surface of the interlayer insulating film.

11. The thin film transistor array substrate of claim 10 , wherein the driving voltage line is formed over a same layer as the second electrode.

12. The thin film transistor array substrate of claim 10 , wherein the driving voltage line and the second electrode are each in direct contact with the interlayer insulating film.

13. The thin film transistor array substrate of claim 9 , wherein the interlayer insulating film is formed of an organic material.

14. The thin film transistor array substrate of claim 9 , wherein at least a portion of the driving TFT overlaps the storage capacitor.

15. The thin film transistor array substrate of claim 9 , wherein at least a portion of the storage capacitor overlaps the driving TFT.

16. An organic light-emitting diode (OLED) display comprising i) a display region comprising a plurality of pixels and ii) a non-display region surrounding the display region, wherein each of the pixels comprises the TFT array substrate of claim 1 .

17. The display of claim 16 , further comprising a first via layer formed over an upper surface of the interlayer insulating film and having first and second opening portions exposing portions of the upper surface of the interlayer insulating film.

18. The display of claim 17 , wherein the second electrode is formed in the first opening portion on the upper surface of the interlayer insulating film, and wherein the driving voltage line is formed in the second opening portion on the upper surface of the interlayer insulating film.

19. The display of claim 17 , further comprising:
a second via layer formed over an upper portion of the first via layer and having a first via hole and a second via hole, and
a bridge formed over an upper portion of the second via layer and electrically connecting the second electrode to the dr

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jungkyu
• Kwon Dohyun
• Kim Taehyun
• Sim Suyeon
• Cho Seunghwan
• Yeo Jongmo
• Lee Joongeol

Classifications

• H01L27/124

  Electricity · mapped topic

• H01L27/1255

  Electricity · mapped topic

• H01L27/3265 Primary

  Electricity · mapped topic

• H10D30/6704 Primary

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title