Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts

Patent metadata

Field	Value
Publication number	US-9768190-B2
Application number	US-201514963280-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Aug 7, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a first electrode structure and a second electrode structure on the upper surface of the substrate that are spaced apart from each other along the second direction;
a plurality of vertical pillars that comprise a first set of vertical pillars and a second set of vertical pillars, the vertical pillars in the first set penetrating through the first electrode structure and the vertical pillars in the second set penetrating through the second electrode structure;
a plurality of lower contacts that vertically overlap and electrically connect to respective ones of the vertical pillars; and
a plurality of sub-interconnections that electrically connect respective ones of the vertical pillars in the first set to respective ones of the vertical pillars in the second set,
wherein central axes of the lower contacts are offset from central axes of the respective vertical pillars that the lower contacts vertically overlap.

2. The semiconductor memory device of claim 1 , further comprising:
a plurality of bit lines extending in the second direction; and
a plurality of upper contacts that electrically connect respective ones of the sub-interconnections to respective ones of the bit lines,
wherein the sub-interconnections extend in the second direction and include respective protruding portions.

3. The semiconductor memory device of claim 2 , wherein the plurality of sub-interconnections comprises a first plurality of sub-interconnections and the plurality of vertical pillars comprises a first plurality of vertical pillars, the semiconductor memory device further comprising:
a third electrode structure on the upper surface of the substrate that is spaced apart from the second electrode structure in the second direction, the second electrode structure being between the first electrode structure and the third electrode structure;
a second plurality of vertical pillars that comprise a third set of vertical pillars and a fourth set of vertical pillars, the vertical pillars in the third set penetrating through the second electrode structure and the vertical pillars in the fourth set penetrating through the third electrode structure; and
a second plurality of sub-interconnections that electrically connect respective ones of the vertical pillars in the third set to respective ones of the vertical pillars in the fourth set.

4. The semiconductor memory device of claim 3 , wherein the protruding portion of a first of the sub-interconnections in the first plurality of sub-interconnections extends in the first direction, and the protruding portion of a first of the sub-interconnections in the second plurality of sub-interconnections extends in a direction opposite the first direction, and wherein the central axes of the lower contacts are offset from the central axes of the respective vertical pillars that the lower contacts vertically overlap in both the first direction and the second direction.

5. The semiconductor memory device of claim 3 , wherein the central axes of first and second of the lower contacts that vertically overlap respective first and second of the vertical pillars that are electrically connected to a first of the sub-interconnections are offset from the central axes of the respective first and second of the vertical pillars in the first direction, and the central axes of third and fourth of the lower contacts that vertically overlap respective third and fourth of the vertical pillars that are electrically connected to a second of the sub-interconnections are offset from the central axes of the respective third and fourth of the vertical pillars in a direction opposite the first direction.

6. The semiconductor memory device of claim 1 , wherein the sub-interconnections are spaced apart from each other in the first direction, and wherein a first of the sub-interconnections has a first length in the second direction and a second of the sub-interconnections that is adjacent the first of the sub-interconnections has a second length in the second direction that is greater than the first length.

7. The semiconductor memory device of claim 6 , wherein the first of the sub-interconnections is electrically connected to a first of the vertical pillars through a first of the lower contacts and the second of the sub-interconnections is electrically connected to a second of the vertical pillars through a second of the lower contacts, and wherein a central axis of the first of the vertical pillars is offset from a central axis of the first of the lower contacts by a first distance and a central axis of the second of the vertical pillars is offset from a central axis of the second of the lower contacts by a second distance, wherein the first distance is greater than the second distance.

8. The semiconductor memory device of claim 2 , wherein the central axes of first and second of the lower contacts that vertically overlap respective first and second of the vertical pillars that are electrically connected to a first of the sub-interconnections are offset from the central axes of the respective first and second of the vertical pillars in the first direction, and wherein the protruding portion of the first of the sub-interconnections extends in the first direction.

9. A semiconductor memory device, comprising:
a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a plurality of vertical pillars that extend above the substrate in a third direction that is perpendicular to the first and second directions, the vertical pillars aligned in a row that extends in the second direction;
a plurality of lower contacts that vertically overlap and electrically connect to respective ones of the vertical pillars; and
a first bit line and a second bit line, the first and second bit lines each extending in the second direction and spaced apart from each other in the first direction;
wherein a first subset of the lower contacts that are electrically connected to the first bit line are aligned in a first row that extends in the second direction and a second subset of the lower contacts that are electrically connected to the second bit line are aligned in a second row that extends in the second direction, the first row being spaced apart from the second row in the first direction.

10. The semiconductor memory device of claim 9 , wherein central axes of the lower contacts are offset from central axes of the respective vertical pillars that the lower contacts vertically overlap.

11. The semiconductor memory device of claim 9 , wherein the vertical pillars are arranged in pairs, the semiconductor memory device further comprising a plurality of sub-interconnections that electrically connect a first vertical pillar of a respective pair to a second vertical pillar of the respective pair.

12. The semiconductor memory device of claim 11 , wherein the sub-interconnections that are electrically connected to the first bit line include respective protruding portions that extend in a direction opposite the first direction and the sub-interconnection that are electrically connected to the second bit line include respective protruding portions that extend in the first direction.

13. The semiconductor memory device of claim 12 , wherein central axes of the lower contacts that are electrically connected to the first bit line are offset from central axes of the respective vertical pillars that the lower contacts vertically o

Assignees

• Lee Taehee
• Kim Kyoung-Hoon
• Kim Hongsoo
• Samsung Electronics Co Ltd

Inventors

• Lee Taehee
• Kim Kyoung-Hoon
• Kim Hongsoo

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10D1/00 Primary

  Resistors, capacitors or inductors · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title