Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9768163-B2
Application number	US-201514744722-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Oct 21, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first gate pattern including a first gate spacer and a second gate pattern including a second gate spacer on a substrate, the first gate pattern including a first capping pattern and having a first height and the second gate pattern including a second capping pattern and having a second height;
an inter-metal dielectric pattern on the substrate covering the first and second gate patterns, the inter-metal dielectric pattern including a trench exposing the substrate between the first and second gate patterns;
a spacer contacting at least a portion of a sidewall of the inter-metal dielectric pattern defining the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights; and
a contact structure in the trench, the contact structure including a metal pattern and a distinct barrier layer,
wherein the spacer is not formed on a first uppermost surface of the first gate pattern and a second uppermost surface of the second gate pattern,
wherein sidewalls of the trench include a recessed portion.

2. The semiconductor device of claim 1 , further comprising a source or a drain between the first gate pattern and the second gate pattern, wherein a top surface of the source or drain is higher than a bottom surface of the first gate pattern or a bottom surface of the second gate pattern, respectively.

3. The semiconductor device of claim 1 , wherein a lower surface of the spacer contacts the substrate.

4. The semiconductor device of claim 1 , wherein a portion of the inter-metal dielectric pattern is between each of the first and second gate patterns and the spacer.

5. The semiconductor device of claim 4 , wherein the spacer and the inter-metal dielectric pattern are made of different materials.

6. The semiconductor device of claim 1 , wherein the contact structure is spaced apart from the first and second gate patterns.

7. The semiconductor device of claim 6 , wherein the contact structure contacts the spacer.

8. A semiconductor device comprising:
a first gate pattern and a second gate pattern on a substrate, the first gate pattern including a first capping pattern and having a first height and the second gate pattern including a second capping pattern and having a second height;
an inter-metal dielectric pattern on the substrate, the inter-metal dielectric pattern covering the first and second gate patterns;
an upper contact pattern between the first and second gate patterns, the upper contact pattern having a first width;
a lower contact pattern on a lower portion of the upper contact pattern between the first and second gate patterns, the lower contact pattern having a second width narrower than the first width and including a metal pattern and a distinct barrier layer; and
a spacer contacting a sidewall of the lower contact pattern, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights,
wherein the spacer is not formed on a first uppermost surface of the first gate pattern and a second uppermost surface of the second gate pattern,
wherein a width of the upper contact pattern and a width of the lower contact pattern are different from each other at an interface between the upper contact pattern and the lower contact pattern.

9. The semiconductor device of claim 8 , wherein the upper contact pattern and the lower contact pattern have a hammer shape.

10. The semiconductor device of claim 8 , wherein the upper contact pattern is spaced apart from the first and second gate patterns.

11. The semiconductor device of claim 8 , wherein a lower surface of the spacer contacts the substrate.

12. The semiconductor device of claim 8 , wherein a portion of the inter-metal dielectric pattern is between each of the first and second gate patterns and the spacer.

13. The semiconductor device of claim 12 , wherein the spacer and the inter-metal dielectric pattern are made of different materials.

14. A semiconductor device comprising:
a first spacer contacting a sidewall of a gate electrode, the first spacer having a first height;
an inter-metal dielectric pattern on the substrate covering the gate electrode and contacting a sidewall of the first spacer;
a second spacer contacting a sidewall of the inter-metal dielectric pattern, the second spacer different from the first spacer and having a second height greater than the first height, the first spacer, the inter-metal dielectric pattern, and the second spacer being sequentially arranged; and
a conductive layer pattern contacting a sidewall of the second spacer,
wherein the second spacer is not formed on an uppermost surface of the gate electrode,
wherein sidewalls of the conductive layer pattern include a protruding portion that does not contact the sidewall of the second spacer,
wherein a width of the protruding portion is wider than a width of an other portion of the conductive layer pattern.

15. The semiconductor device of claim 14 , wherein the first spacer includes silicon nitride, silicon oxynitride, silicon oxide, and/or silicon carbon oxynitride.

16. The semiconductor device of claim 14 , wherein the second spacer and the inter-metal dielectric pattern are made of different materials.

17. The semiconductor device of claim 14 , wherein the conductive layer pattern has a hammer shape.

18. The semiconductor device of claim 14 , wherein the conductive layer pattern is spaced apart from the first spacer.

Assignees

• Lee Doo-Young
• Lee Sang-Hyun
• Jung Myung-Hoon
• Kim Do-Hyoung
• Samsung Electronics Co Ltd

Inventors

• Lee Doo-Young
• Lee Sang-Hyun
• Jung Myung-Hoon
• Kim Do-Hyoung

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title