Semiconductor device assembly with heat transfer structure formed from semiconductor material

Patent metadata

Field	Value
Publication number	US-9768149-B2
Application number	US-201514716176-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	May 19, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a thermal transfer structure formed from a semiconductor material, wherein the thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions;
a stack of first semiconductor dies in the cavity; and
a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity,
wherein the outer region of the thermal transfer structure includes a sidewall surface separated from the stack of first semiconductor dies by a gap, and wherein the semiconductor device assembly further comprises an underfill material having a fillet in the gap.

2. The semiconductor device assembly of claim 1 wherein the first and second semiconductor dies and the semiconductor material of the thermal transfer structure each comprise a silicon material.

3. The semiconductor device assembly of claim 1 wherein the first and second semiconductor dies are electrically isolated from the semiconductor material of the thermal transfer structure.

4. The semiconductor device assembly of claim 1 wherein the semiconductor material of the thermal transfer structure has a first coefficient of thermal expansion (CTE), and wherein the second semiconductor die has a second CTE that is generally the same as the first CTE.

5. The semiconductor device assembly of claim 4 wherein each of the first semiconductor dies has a third CTE that is generally the same as the first CTE.

6. The semiconductor device assembly of claim 1 wherein the second semiconductor die includes an exposed surface in the gap.

7. The semiconductor device assembly of claim 1 , wherein the outer region of the thermal transfer structure includes a recessed portion and a raised portion peripheral to the recessed portion and forming a support feature with the recessed portion, and wherein the second semiconductor die includes a peripheral region attached to the recessed portion and adjacent the raised portion of the support feature.

8. The semiconductor device assembly of claim 7 , further comprising a package support substrate attached to the second semiconductor die, and having a peripheral portion attached to the raised portion of the support feature of the thermal transfer structure.

9. A semiconductor device assembly, comprising:
a thermal transfer structure formed from a semiconductor material, wherein the thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions;
a stack of first semiconductor dies in the cavity; and
a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity,
wherein the inner region of the thermal transfer structure has a thickness of from about 50 μm to about 200 μm.

10. The semiconductor device assembly of claim 9 wherein each of the first semiconductor dies has a thickness of from about 50 μm to about 200 μm.

11. The semiconductor device assembly of claim 9 , further comprising a thermal interface material between the outer region of the thermal transfer structure and the second semiconductor die.

12. The semiconductor device assembly of claim 9 , further comprising a thermal interface material between the inner region of the thermal transfer structure and the stack of first semiconductor dies.

13. The semiconductor device assembly of claim 9 wherein the first semiconductor dies are memory dies, and wherein the second semiconductor die is a logic die.

14. The semiconductor device assembly of claim 9 wherein the first and second semiconductor dies and the semiconductor material of the thermal transfer structure each comprise a silicon material.

15. The semiconductor device assembly of claim 14 wherein the thermal transfer structure is not formed from metal.

16. The semiconductor device assembly of claim 13 , further comprising a package support substrate attached and electrically coupled to the logic die, wherein the logic die includes a plurality of through-silicon vias extending through the base region and electrically coupling the package support substrate to one or more of the memory dies.

17. A method of forming a semiconductor device assembly, comprising:
attaching a stack of first semiconductor dies to a recessed surface in a cavity of a semiconductor wafer comprising semiconductor material;
covering an opening of the cavity with a second semiconductor die having a peripheral region that attaches to a portion of the outer surface that is adjacent the cavity; and
singulating the semiconductor wafer to define a thermal transfer structure comprised of the semiconductor material that encloses the stack of semiconductor dies with the second semiconductor die.

18. The method of claim 17 , further comprising:
depositing an underfill material between individual first semiconductor dies of the stack of first semiconductor dies; and
accumulating excess underfill material between the stack of first semiconductor dies and a sidewall surface in the cavity adjacent the recessed surface.

19. The method of claim 17 wherein the semiconductor material comprises silicon.

20. The method of claim 17 wherein singulating the semiconductor wafer includes singulating the semiconductor wafer after attaching the stack of first semiconductor dies to the recessed surface in the cavity.

21. The method of claim 17 further comprising attaching the peripheral region of the second semiconductor die to the portion of the outer surface, wherein singulating the semiconductor wafer includes singulating the semiconductor wafer after attaching the second semiconductor die.

22. The method of claim 17 , further comprising attaching a package support substrate to the second semiconductor die, wherein singulating the semiconductor wafer includes singulating the semiconductor wafer after attaching the package support substrate.

23. The method of claim 17 wherein the first semiconductor dies comprise memory dies, and wherein the second semiconductor die comprises a logic die.

24. A method of forming a semiconductor device assembly, comprising:
forming a thermal transfer structure from a semiconductor substrate, wherein the thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions;
positioning a stack of memory dies in the cavity of the thermal transfer structure;
attaching a base region of a logic die to an outermost memory die of the stack of memory dies;
attaching a peripheral region of the logic die to the outer region of the thermal transfer structure; and
thinning the inner region of the thermal transfer structure to a thickness of 200 μm or less.

25. The method of claim 24 , further comprising forming a recessed portion in the outer region of the thermal transfer structure and adjacent the cavity, and wherein attaching the peripheral region of the logic die to the outer region includes attaching the peripheral region to the recessed portion.

26. The method of claim 25 , further comprising attaching a package support substrate to the logic die and a raised portion of the thermal tr

Assignees

• Micron Technology Inc

Inventors

• Vadhavkar Sameer S
• Gandhi Jaspreet S
• Derderian James M

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title