Semiconductor devices having nonlinear bitline structures

Patent metadata

Field	Value
Publication number	US-9768115-B2
Application number	US-201514701777-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	May 21, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of nonlinear bit lines on a substrate including a plurality of active areas;
a plurality of word lines passing through the plurality of active areas in the substrate;
integral spacers on two sidewalls of the plurality of nonlinear bit lines and that define a plurality of spaces that expose two adjacent ones of the plurality of active areas;
two conductive patterns that respectively abut on the two adjacent ones of the plurality of active areas in a space that is selected from the plurality of spaces; and
contact separating insulation layers between the two conductive patterns in the space that is selected,
wherein the integral spacers separate the two conductive patterns and the contact separating insulation layers from the plurality of nonlinear bit lines.

2. The semiconductor device of claim 1 :
wherein the plurality of nonlinear bit lines comprise a first bit line portion that overlaps at least one of the plurality of active areas in parallel; and
wherein a length of the first bit line portion is no less than a pitch of the plurality of word lines.

3. The semiconductor device of claim 2 , wherein the first bit line portion overlaps two adjacent ones of the plurality of word lines.

4. The semiconductor device of claim 1 :
wherein the plurality of nonlinear bit lines comprise a first bit line portion that overlaps at least one of the plurality of active areas in parallel; and
wherein a length of the first bit line portion is equal to or greater than a distance between two adjacent ones of the plurality of word lines.

5. The semiconductor device of claim 4 , wherein the first bit line portion does not overlap the plurality of word lines.

6. The semiconductor device of claim 1 :
wherein the plurality of nonlinear bit lines comprise a first bit line portion that crosses and overlaps at least one of the plurality of active areas and a second bit line portion that does not overlap the plurality of active areas; and
wherein a length of the second bit line portion is equal to or greater than a pitch of the plurality of word lines.

7. The semiconductor device of claim 6 , further comprising a direct contact that overlaps the first bit line portion and connects the plurality of nonlinear bit lines and the plurality of active areas.

8. The semiconductor device of claim 6 , wherein the second bit line portion overlaps two adjacent ones of the plurality of word lines.

9. The semiconductor device of claim 1 , wherein a distance between a bottom surface and an upper surface of each of the plurality of nonlinear bit lines is smaller than a distance between a bottom surface and an upper surface of each of the integral spacers.

10. The semiconductor device of claim 1 , wherein a distance between a bottom surface and an upper surface of the contact separating insulation layers is greater than a distance between a bottom surface and an upper surface of the integral spacers.

11. The semiconductor device of claim 1 , further comprising two landing pads respectively abutting on the two conductive patterns on the two conductive patterns.

12. A semiconductor device comprising:
a pair of nonlinear bit lines on a substrate including a plurality of active areas and that are symmetrically-shaped;
a plurality of word lines that pass through the plurality of active areas of the substrate;
integral spacers on sidewalls of the pair of the nonlinear bit lines in an area between the pair of nonlinear bit lines and that include a plurality of spaces that are arranged in a row;
two conductive patterns in one space that is selected from the plurality of spaces and are spaced apart from each other; and
a contact separating insulation layer between the two conductive patterns in the one space that is selected,
wherein the integral spacers separate the two conductive patterns and the contact separating insulation layers from the pair of nonlinear bit lines.

13. The semiconductor device of claim 12 :
wherein the pair of nonlinear bit lines have at least one inflection point; and
wherein the at least one inflection point is located at a portion where the pair of nonlinear bit lines overlap the plurality of word lines.

14. The semiconductor device of claim 12 , wherein a distance between the pair of nonlinear bit lines is varied in a length direction of the pair of nonlinear bit lines.

15. The semiconductor device of claim 12 , wherein the contact separating insulation layer overlaps the plurality of word lines.

16. A semiconductor device comprising:
a plurality of nonlinear bit lines on a substrate including a plurality of active areas;
a plurality of word lines passing through the plurality of active areas in the substrate;
integral spacers on two sidewalls of the plurality of nonlinear bit lines and that define a plurality of spaces that expose two adjacent ones of the plurality of active areas;
two conductive patterns that respectively abut on the two adjacent ones of the plurality of active areas in a space that is selected from the plurality of spaces;
contact separating insulation layers between the two conductive patterns in the space that is selected; and
a contact that connects each of the plurality of active areas and a capacitor, wherein the contact and the capacitor are formed using a self-alignment process without an exposure process,
wherein the integral spacers separate the two conductive patterns and the contact separating insulation layers from the plurality of nonlinear bit lines.

17. The semiconductor device of claim 16 :
wherein the plurality of nonlinear bit lines comprise a first bit line portion that overlaps at least one of the plurality of active areas in parallel; and
wherein a length of the first bit line portion is equal to or greater than a distance between two adjacent ones of the plurality of word lines.

18. The semiconductor device of claim 17 , wherein the first bit line portion does not overlap the plurality of word lines.

19. The semiconductor device of claim 16 , wherein a distance between a bottom surface and an upper surface of each of the plurality of nonlinear bit lines is smaller than a distance between a bottom surface and an upper surface of each of the integral spacers.

20. The semiconductor device of claim 16 , wherein a distance between a bottom surface and an upper surface of the contact separating insulation layers is greater than a distance between a bottom surface and an upper surface of the integral spacers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yunjung
• Im Kivin
• Lee Dongbok
• Hwang Inseak

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L27/10814

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L27/115

  Electricity · mapped topic