Physical unclonable interconnect function array

Patent metadata

Field	Value
Publication number	US-9768110-B2
Application number	US-201615060685-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Mar 8, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

First claim

What is claimed is:

1. A method for fabricating an interconnect function array, the method comprising:
forming a first plurality of conductive lines in a substrate;
forming an insulator layer over the first plurality of conductive lines and the substrate;
removing portions of the insulator layer to define cavities in the insulator layer, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines;
depositing a dielectric layer over the insulator layer and the cavities; and
forming a second plurality of conductive lines in the dielectric layer.

2. The method of claim 1 , wherein the method comprises forming a photolithographic resist layer over the insulator layer by depositing a layer of photolithographic resist material that includes an impurity that results in a substantially random pattern in the photolithographic resist layer corresponding to the substantially random arrangement of cavities following development of the photolithographic resist layer that exposes portions of the insulator layer prior to removing the portions of the insulator layer.

3. The method of claim 1 , wherein the forming the second plurality of conductive lines includes:
patterning the dielectric layer with a photolithographic resist material;
removing portions of the photolithographic resist material to expose portions of the dielectric layer;
removing exposed portions of the dielectric layer to define channels in the dielectric layer;
depositing a conductive material in the channels.

4. The method of claim 3 , further comprising removing excess portions of the conductive material that are deposited on the dielectric layer from the dielectric layer by applying a chemical-mechanic-polishing (CMP) process.

5. The method of claim 1 , wherein conductive lines of the first plurality of conductive lines are arranged such that each of the conductive lines are arranged substantially parallel to each other.

6. The method of claim 5 , wherein conductive lines of the second plurality of conductive lines are arranged such that each of the conductive lines are arranged substantially parallel to each other.

7. The method of claim 1 , wherein the second plurality of conductive lines overlap portions of the first plurality of conductive lines and lines of the first plurality of conductive lines are arranged substantially orthogonal relative to lines of the second plurality of lines.

8. The method of claim 1 , wherein the cavities are filled with a dielectric material.

Assignees

• IBM

Inventors

• Feng Kai D
• Li Wai-Kin
• Wang Ping-Chuan
• Yang Zhijian

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title