Integrated circuit packaging system with support structure and method of manufacture thereof

US9768102B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9768102-B2
Application numberUS-201213425768-A
CountryUS
Kind codeB2
Filing dateMar 21, 2012
Priority dateMar 21, 2012
Publication dateSep 19, 2017
Grant dateSep 19, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacture of an integrated circuit packaging system comprising: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having an attachment pad, a redistribution pad, a vertical connector, and an insulation, the redistribution pad having a vertical height greater than a vertical height of the attachment pad and only at an insulation top side of the insulation, and the vertical connector having a height greater than a height of the redistribution pad, coplanar with a bottom side of the insulation, directly on the redistribution pad, within the insulation, and having a bottom width greater than a top width; mounting an integrated circuit over the one-layer substrate, the integrated circuit having an inactive side attached to the insulation top side of the insulation; and forming an encapsulation over the integrated circuit. 2. The method as claimed in claim 1 wherein forming the one-layer substrate includes forming the one-layer substrate having the attachment pad coplanar with the insulation. 3. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting the integrated circuit over the one-layer substrate with the redistribution pad directly under the integrated circuit. 4. The method as claimed in claim 1 wherein forming the one-layer substrate includes forming the one-layer substrate having the attachment pad only at the insulation top side of the insulation. 5. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting the integrated circuit over the one-layer substrate with the attachment pad only outside a non-horizontal extent of the integrated circuit. 6. A method of manufacture of an integrated circuit packaging system comprising: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having an attachment pad, a redistribution pad, a vertical connector, and an insulation, the redistribution pad having a vertical height greater than a vertical height of the attachment pad and only at an insulation top side of the insulation, and the vertical connector having a height greater than a height of the redistribution pad, coplanar with a bottom side of the insulation, directly on the redistribution pad, within the insulation, and having a bottom width greater than a top width; mounting an integrated circuit over the one-layer substrate, the integrated circuit having an inactive side attached to the insulation top side of the insulation; and forming an encapsulation over the integrated circuit. 7. The method as claimed in claim 6 wherein forming the one-layer substrate includes forming the one-layer substrate having the attachment pad having an attachment pad top side coplanar with the insulation top side of the insulation. 8. The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting the integrated circuit over the one-layer substrate with the redistribution pad and the vertical connector directly under the integrated circuit. 9. The method as claimed in claim 6 wherein forming the one-layer substrate includes forming the one-layer substrate having the attachment pad only at the insulation top side of the insulation, the attachment pad electrically connected to the redistribution pad. 10. The method as claimed in claim 6 wherein: mounting the integrated circuit includes mounting the integrated circuit over the one-layer substrate with the attachment pad only outside a non-horizontal extent of the integrated circuit; and further comprising: attaching an internal connector to the integrated circuit and the attachment pad. 11. An integrated circuit packaging system comprising: a one-layer substrate with a symmetrical structure, the one-layer substrate having an attachment pad, a redistribution pad, a vertical connector, and an insulation, the redistribution pad having a vertical height greater than a vertical height of the attachment pad and only at an insulation top side of the insulation, and the vertical connector having a height greater than a height of the redistribution pad, coplanar with a bottom side of the insulation, directly on the redistribution pad, within the insulation, and having a bottom width greater than a top width; an integrated circuit over the one-layer substrate, the integrated circuit having an inactive side attached to the insulation top side of the insulation; and an encapsulation over the integrated circuit. 12. The system as claimed in claim 11 wherein the one-layer substrate includes the attachment pad coplanar with the insulation. 13. The system as claimed in claim 11 wherein the integrated circuit is over the one-layer substrate with the redistribution pad directly under the integrated circuit. 14. The system as claimed in claim 11 wherein the one-layer substrate includes the attachment pad only at the insulation top side of the insulation. 15. The system as claimed in claim 11 wherein the integrated circuit is over the one-layer substrate with the attachment pad only outside a non-horizontal extent of the integrated circuit. 16. The system as claimed in claim 11 wherein the one-layer substrate includes the attachment pad having an attachment pad top side coplanar with the insulation top side of the insulation. 17. The system as claimed in claim 11 wherein the integrated circuit is over the one-layer substrate with the redistribution pad and the vertical connector directly under the integrated circuit. 18. The system as claimed in claim 11 wherein the one-layer substrate includes the attachment pad only at the insulation top side of the insulation, the attachment pad electrically connected to the redistribution pad. 19. The system as claimed in claim 11 wherein: the integrated circuit is over the one-layer substrate with the attachment pad only outside a non-horizontal extent of the integrated circuit; and further comprising: an internal connector attached to the integrated circuit and the attachment pad.

Assignees

Inventors

Classifications

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • the substrate having spherical bumps for external connection · CPC title

  • of vias therein · CPC title

  • H10W70/635Primary

    Through-vias · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9768102B2 cover?
A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.
Who is the assignee on this patent?
Jeon Dong Ju, Lee Koo Hong, Kim Sung Soo, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).