Wafer stack protection seal

Patent metadata

Field	Value
Publication number	US-9768089-B2
Application number	US-201615224680-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Mar 13, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing first and second wafers of a wafer stack, the first and second wafers having first and second major surfaces, the wafers include edge and non-edge regions, wherein the first and second wafers include devices formed in the non-edge region, the first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack;
forming device seals on the first major surfaces of the first and second wafers in the non-edge region, wherein the device seals surround the devices in the non-edge region of the first and second wafers;
bonding the first and second wafers to form the wafer stack, wherein the first major surfaces of the first and second wafers face each other and the device seals are aligned for bonding;
forming a step edge of the wafer stack such that the base wafer is wider than the top wafer in the wafer stack to provide the step edge; and
forming an edge protection seal covering the step edge of the wafer stack comprising
depositing a first layer on the wafer stack including at the top wafer and step edge of the wafer stack, wherein the first layer covers the second major surface of the top wafer completely and peripheral side of the top wafer, gap between the top and base wafers and a portion of the base wafer, and
depositing a second layer on the wafer stack, wherein the second layer is deposited over the first layer at the top wafer and step edge of the wafer stack, wherein the portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

2. The method of claim 1 further comprising patterning the first layer to form openings prior to depositing the second layer.

3. The method of claim 2 wherein the portion of the first layer deposited on the top wafer of the wafer stack serves as a redistribution layer of the top wafer.

4. The method of claim 1 further comprising back grinding the top wafer to expose TSV contacts in the top wafer.

5. The method of claim 1 wherein forming the step edge of the wafer stack comprises trimming the top wafer of the wafer stack such that the base wafer is wider than the top wafer by a first width from the peripheral side of the top wafer to provide the step edge.

6. The method of claim 1 wherein the first layer deposited on the wafer stack is a metal layer.

7. The method of claim 1 wherein the first layer is deposited by sputtering.

8. The method of claim 1 further comprising patterning the second layer.

9. The method of claim 8 wherein the portion of the second layer deposited over the top wafer of the wafer stack further serves as a passivation layer of the top wafer.

10. The method of claim 1 wherein the second layer deposited on the wafer stack is a dielectric layer.

11. The method of claim 1 further comprising depositing an isolation layer on the top wafer of the wafer stack and patterning the isolation layer to form openings corresponding to through silicon vias in the top wafer prior to depositing the first layer on the wafer stack.

12. A method of forming a semiconductor device comprising:
providing first and second wafers of a wafer stack, the first and second wafers having first and second major surfaces, the wafers include edge and non-edge regions, wherein the first and second wafers include devices formed in the non-edge region, the first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack;
forming device seals on the first major surfaces of the first and second wafers in the non-edge region, wherein the device seals surround the devices in the non-edge region of the first and second wafers;
bonding the first and second wafers to form the wafer stack, wherein the first major surfaces of the first and second wafers face each other and the device seals are aligned for bonding;
trimming the wafer stack, wherein a portion of the top wafer is trimmed such that the base wafer is wider than the top wafer by a first width from the peripheral side of the trimmed top wafer, forming a step edge of the wafer stack; and
forming an edge protection seal covering the step edge of the wafer stack, wherein forming the edge protection seal comprises depositing a first layer on the wafer stack including the top wafer and step edge of the wafer stack, wherein the first layer covers the second major surface of the top wafer completely and peripheral side of the top wafer, gap between the top and base wafers and a portion of the base wafer, wherein the first layer on the peripheral side of the top wafer, gap between the top and base wafers and the portion of the base wafer protects the devices of the wafer stack in subsequent processing.

13. The method of claim 12 wherein forming the edge protection seal further comprises depositing a second layer on the first layer of the wafer stack, wherein the second layer is deposited over the top wafer and step edge of the wafer stack, the portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in subsequent processing.

14. The method of claim 12 further comprising back grinding the top wafer to expose TSV contacts in the top wafer.

15. The method of claim 12 wherein the portion of the first layer deposited on the second major surface of the top wafer of the wafer stack serves as a redistribution layer of the top wafer and the portion of the second layer deposited on the first layer over the second major surface of the top wafer serves as a passivation layer.

16. The method of claim 15 wherein the first layer deposited on the wafer stack is formed of metal.

17. The method of claim 15 wherein the second layer deposited on the wafer stack is a dielectric layer.

18. A semiconductor wafer stack, comprising:
first and second wafers bonded together on their first major surfaces, the wafers include edge and non-edge regions, wherein the first and second wafers include devices and device seals that surround the devices in the non-edge region, the device seals are disposed on the first major surfaces of the first and second wafers, the first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, wherein the base wafer is wider than the top wafer by a first width from the peripheral side of the top wafer, providing a step edge of the wafer stack; and
an edge protection seal disposed on the wafer stack covering the step edge and protects the devices in the wafer stack in subsequent processing, wherein the edge protection seal comprises a first layer disposed on the step edge of the wafer stack covering a gap between the top and base wafers and extends to a portion of the base wafer.

19. The semiconductor wafer of claim 18 wherein the first layer further covers a second major surface of the top wafer of the wafer stack completely and serves as a redistribution layer on the top wafer.

20. The semiconductor wafer of claim 19 wherein the edge protection seal further comprises a second layer disposed over the first layer on the step edge of the wafer stack covering the gap between the top and base wafers and extends to the portion of the base wafer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Rajoo Ranjan
• Chan Kai Chong

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title