Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9768018-B2
Application number	US-201615097369-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Aug 28, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming sub-stack structures sequentially stacked on a substrate;
forming an active pillar sequentially penetrating the sub-stack structures, wherein forming the active pillar comprises forming an active plug adjacent the substrate and an active shell having a hollow cup-shape on the active plug; and
increasing a grain size of the active pillar by a metal induced lateral crystallization operation,
wherein increasing the grain size of the active pillar comprises:
forming a metal silicide layer including a crystallization inducing metal on a top surface of the active pillar; and
performing an annealing process to diffuse the crystallization inducing metal into the active pillar, wherein a concentration of the crystallization inducing metal at a bottom surface of the active shell is higher than a concentration of the crystallization inducing metal at a sidewall of the active shell.

2. The method of claim 1 , wherein the active pillar includes poly-silicon having the grain size of about 1 μm or more.

3. The method of claim 1 , wherein forming the active pillar comprises:
forming sacrificial plugs respectively penetrating the sub-stack structures, the sacrificial plugs vertically overlapping with each other;
removing the sacrificial plugs; and
forming the active pillar in empty regions formed by the removal of the sacrificial plugs.

4. The method of claim 3 , wherein each of the sub-stack structures includes sacrificial layers and insulating layers which are alternately stacked,
the method further comprising:
forming sacrificial lines spaced apart from the sacrificial plugs, the sacrificial lines respectively penetrating the sub-stack structures, and the sacrificial lines vertically overlapping with each other;
removing the sacrificial lines to form a groove;
removing the sacrificial layers through the groove;
filling spaces formed by the removal of the sacrificial layers with a conductive layer; and

forming a buried insulation layer in the groove.

5. A method of fabricating a semiconductor device, the method comprising:
forming sub-stack structures sequentially stacked on a substrate;
forming an active pillar sequentially penetrating the sub-stack structures,
wherein forming the active pillar comprises forming an active plug adjacent the substrate and sub-active pillars on the active plug and the active plug and the sub-active pillars constitute the active pillar, and wherein the sub-active pillars penetrate the sub-stack structures and comprise sub-active shells of hollow cup-shapes, respectively; and
increasing a grain size of the active pillar by a metal induced lateral crystallization operation,
wherein increasing the grain size of the active pillar comprises:
forming a metal silicide layer including a crystallization inducing metal on a top surface of each of the sub-active pillars; and
performing an annealing process to diffuse the crystallization inducing metal into each of the sub-active pillars, wherein a concentration of the crystallization inducing metal at a bottom surface of a lowermost sub-active shell is higher than a concentration of the crystallization inducing metal at a sidewall of the sub-active shells.

6. The method of claim 5 , wherein each of the sub-stack structures includes conductive layers and insulating layers that are alternately stacked,
wherein a sidewall of the active pillar adjacent an interface between the sub-stack structures is substantially non-linear.

7. The method of claim 5 , wherein each of the sub-stack structures includes sacrificial layers and insulating layers which are alternately stacked,
the method further comprising:
removing portions of the sub-stack structures spaced apart from the active pillar to form a groove;
removing the sacrificial layers through the groove;
filling spaces formed by the removal of the sacrificial layers with a conductive layer; and
forming a buried insulation layer in the groove.

8. The method of claim 1 wherein forming the active pillar further comprises forming a first active pad disposed on a top end of the active pillar and having a disk-shaped plane.

9. The method of claim 5 , wherein the sub-active pillars further comprise sub-active pads on the substrate, respectively.

10. The method of claim 5 , wherein a concentration of the crystallization inducing metal at an interface between the sub-active pillars is higher than a concentration of the crystallization inducing metal at a sidewall of the sub-active pillars.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Yujeong
• Park Jintaek
• Park Youngwoo

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10P14/3806 Primary

  using crystallisation-enhancing elements · CPC title

• H10D62/40

  Crystalline structures · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title