Semiconductor memory devices and memory systems including the same

Patent metadata

Field	Value
Publication number	US-9767920-B2
Application number	US-201514798634-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Aug 11, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main data, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array;
an input/output (I/O) gating circuit configured to read test pattern data from the memory cell array to provide test result data in a test mode, and configured to read a codeword from the memory cell array in a normal mode;
an error decision circuit configured to determine correctability of errors in the test result data according to a first unit of data whose size is equal to or smaller than a size of the codeword, based on the test pattern data and the test result data, and the error decision circuit configured to provide a first error kind signal indicating a first determination result, in the test mode; and
an error check and correction (ECC) circuit configured to decode the codeword, the codeword including main data and parity data generated from the main data, the ECC circuit configured to determine correctability of errors in the codeword according to a second unit of data whose size is equal to or smaller than the size of the codeword, and the ECC circuit configured to provide a second error kind signal indicating a second determination result, in the normal mode, and
wherein the main data includes a plurality of units of data.

2. The semiconductor memory device of claim 1 , wherein the error decision circuit is configured to be enabled in response to a mode signal indicating the test mode.

3. The semiconductor memory device of claim 1 , wherein
the error decision circuit includes,
a first buffer configured to store the test pattern data;
a second buffer configured to store the test result data;
a comparator circuit configured to compare corresponding bits of the test pattern data and the test result data, and to output comparison result data; and
an error counter block configured to provide the first error kind signal based on the comparison result data.

4. The semiconductor memory device of claim 3 , wherein
the comparator circuit includes a plurality of comparators,
each of the plurality of comparators is configured to compare a corresponding bit of the test pattern data and the test result data and is configured to output a bit of the comparison result data; and

the error counter block includes,
a plurality of error counters, each of the plurality of error counters configured to count a number of errors based on the comparison result data, and
a logic unit configured to provide the first error kind signal based on output of the plurality of error counters.

5. The semiconductor memory device of claim 3 , wherein the error decision circuit is configured to output the first error kind signal with a first logic level when a number of errors in the test result data is zero or within an error correction capability of the ECC circuit.

6. The semiconductor memory device of claim 3 , wherein the error decision circuit is configured to output the first error kind signal with a second logic level when a number of errors in the test result data exceeds an error correction capability of the ECC circuit.

7. The semiconductor memory device of claim 1 , wherein
the ECC circuit includes,
an encoder configured to receive the main data to generate the parity data and provide the codeword to the I/O gating circuit; and
a decoder configured to receive the codeword from the I/O gating circuit and detect one or more errors in the main data using the parity data.

8. The semiconductor memory device of claim 7 , wherein
the decoder includes,
a syndrome generator configured to generate syndromes based on the main data and the parity data;
an error position detector configured to detect a position of the one or more errors in the main data based on the syndromes;
an error corrector configured to correct the one or more errors in the main data based on the position of the one or more errors to provide a corrected main data; and
an error signal generator configured to generate the second error kind signal based on the position of the one or more errors.

9. The semiconductor memory device of claim 1 , further comprising:
a register unit configured to store the first error kind signal and a first fail address associated with the first error kind signal in the test mode, and
the register unit configured to store the second error kind signal and a second fail address associated with the second error kind signal in the normal mode.

10. The semiconductor memory device of claim 9 , wherein
the register unit includes,
a register configured to store the first error kind signal and the second error kind signal; and
a fail address table configured to store the first fail address and the second fail address.

11. A memory system comprising:
a semiconductor memory device; and
a memory controller configured to control the semiconductor memory device, the semiconductor memory device including,
a memory cell array having a normal cell array and a redundancy cell array;
an input/output (I/O) gating circuit configured to write a codeword in the memory cell array and configured to read the codeword from the memory cell array;
an error check and correction (ECC) circuit configured to encode main data, the main data including a plurality of units of data to generate parity data,
the ECC circuit configured to provide the codeword, the codeword including the main data and the parity data, to the I/O gating circuit,
the ECC circuit configured to decode the codeword,
the ECC circuit configured to determine correctability of one or more errors in the codeword by an error unit whose size is equal to or smaller than a size of the codeword, and
the ECC circuit configured to provide an error kind signal indicating a determination result, in a normal mode; and

a register unit configured to store the error kind signal and a fail address associated with the error kind signal and configured to provide the error kind signal and the fail address associated with the one or more errors to the memory controller as an error information signal.

12. The memory system of claim 11 , wherein the memory controller is configured to determine an error repair policy that handles the one or more errors in the codeword based on the error information signal.

13. The memory system of claim 12 , wherein the memory controller is configured to determine the error repair policy such that the one or more errors are handled by the error unit whose size is equal to or smaller than the size of the codeword, and
when the errors are handled by the error unit whose size is equal to or smaller than the size of the codeword, a size of the error unit by which the errors are handled is greater than or equal to a size of the unit of data.

14. The memory system of claim 13 , wherein when the error unit by which the one or more errors are handled includes errors exceeding an error correction capability of the ECC circuit, the memory controller is configured to control the semiconductor memory device such that the semiconductor memory device handles the errors exceeding the error correction capability using the redundancy cell array.

15. The memory system of claim 13 , wherein when the error unit by which the one or more errors are handled includes errors within an error correction capability of the ECC circuit, the memory controller is configured to control the semiconductor memory device such that the semiconductor memory device handles the errors using the ECC circuit.

16. A system for error checking semiconductor memory comprising:
an I/O gating circuit configured to write test pattern data into a memory array, and configured to read

Assignees

• Kim Young-Il
• Chung Hoi-Ju
• Samsung Electronics Co Ltd

Inventors

• Kim Young-Il
• Chung Hoi-Ju

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title