Variable rate parallel to serial shift register
US-9076506-B2 · Jul 7, 2015 · US
Scan chain circuits in non-volatile memory
US9767905B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9767905-B2 |
| Application number | US-201514919154-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 21, 2015 |
| Priority date | Oct 21, 2015 |
| Publication date | Sep 19, 2017 |
| Grant date | Sep 19, 2017 |
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Abstract
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A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a plurality of scan block groups comprising a scan chain for a string of binary data, wherein each scan block group includes a first scan block having a first tag bit and a second scan block having a second tag bit, the first scan block of each scan block group having a first input coupled to a first clock signal and the second scan block of each scan block group having a second input coupled to a second clock signal, the first scan…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9767905B2 cover?
- A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token si…
- Who is the assignee on this patent?
- Sandisk 3D Llc, Sandisk Technologies Llc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0483. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).