Redundancy memory device comprising a plurality of selecting circuits

Patent metadata

Field	Value
Publication number	US-9767863-B2
Application number	US-201615066685-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Sep 11, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

According to one embodiment, a memory device includes: a first storage area configured to store data; a first sense amplifier; a first data latch; a first selector configured to select either connection between the first data latch and the first sense amplifier or connection between the first data latch and another sense amplifier; and a second selector configured to select either connection between the first storage area and the first sense amplifier or connection between another storage area and the first sense amplifier.

First claim

What is claimed is:

1. A memory device comprising:
a first storage area configured to store data;
a first sense amplifier;
a first data latch;
a first selector configured to selectively switch between a first connection and a second connection, the first connection being between the first data latch and the first sense amplifier, and the second connection being between the first data latch and another sense amplifier; and
a second selector configured to selectively switch between a third connection and a fourth connection, the third connection being between the first storage area and the first sense amplifier, and the fourth connection being between another storage area and the first sense amplifier.

2. The memory device of claim 1 , wherein:
the another sense amplifier is a redundancy sense amplifier, and
the another storage area is a redundancy storage area.

3. The memory device of claim 1 , further comprising:
a second storage area, which is the another storage area;
a second sense amplifier, which is the another sense amplifier; and
a third selector configured to selectively switch between a fifth connection and a sixth connection, the fifth connection being between the second sense amplifier and the second storage area, and the sixth connection being between the second sense amplifier and the first storage area.

4. The memory device of claim 3 , further comprising:
a third storage area;
a third sense amplifier;
a second data latch;
a fourth selector configured to selectively switch between a seventh connection and a eighth connection, the seventh connection being between the second data latch and the third sense amplifier, and the eighth connection being between the second data latch and the first sense amplifier; and
a fifth selector configured to selectively switch between a ninth connection and a tenth connection, the ninth connection being between the third sense amplifier and the third storage area, and the tenth connection being between the third sense amplifier and the first storage area,
wherein the second selector is further configured to selectively switch between the third connection, the fourth connection, and an eleventh connection, the eleventh connection being between the first sense amplifier and the third storage area.

5. The memory device of claim 4 , wherein, if the first storage area is unusable:
the first selector selects the first connection,
the second selector selects the fourth connection,
the fourth selector selects the seventh connection, and
the fifth selector selects the ninth connection.

6. The memory device of claim 4 , wherein, if the first sense amplifier is unusable:
the first selector selects the second connection,
the third selector selects the sixth connection,
the fourth selector selects the seventh connection, and
the fifth selector selects the ninth connection.

7. The memory device of claim 4 , wherein, if the first storage area and the second sense amplifier are unusable:
the first selector selects the first connection,
the second selector selects the fourth connection,
the fourth selector selects the seventh connection, and
the fifth selector selects the ninth connection.

8. The memory device of claim 4 , wherein, if the second storage area and the first sense amplifier are unusable:
the first selector selects the second connection,
the third selector selects the sixth connection,
the fourth selector selects the seventh connection, and
the fifth selector selects the ninth connection.

9. The memory device of claim 4 , wherein:
upon receipt of a first signal, the first selector selects the second connection, and
upon receipt of the first signal, the fourth selector selects the eighth connection and supplies the first signal to the first selector.

10. The memory device of claim 4 , wherein:
upon receipt of a second signal, the second selector selects the fourth connection and supplies the second signal to the third selector, and
upon receipt of the second signal, the fifth selector selects the tenth connection and supplies the second signal to the second selector.

11. The memory device of claim 10 , wherein:
upon receipt of a third signal, the second selector does not select the fourth connection and does not supply the second signal to the third selector, even if the second selector receives the second signal, and
upon receipt of the third signal, the fifth selector does not select the tenth connection and does not supply the second signal to the second selector, even if the fifth selector receives the second signal.

12. The memory device of claim 4 , wherein:
upon receipt of a fourth signal, the second selector selects the eleventh connection and supplies the fourth signal to the third selector,
upon receipt of the fourth signal, the third selector selects the sixth connection, and
upon receipt of the fourth signal, the fifth selector is further configured to select a twelfth connection, the twelfth connection being between the third sense amplifier and a fourth storage area, and to supply the fourth signal to the second selector.

13. The memory device of claim 12 , wherein:
upon receipt of a fifth signal, the second selector selects the third connection and does not supply the fourth signal to the third selector even if the second selector receives the fourth signal,
upon receipt of the fifth signal, the third selector selects the fifth connection, and
upon receipt of the fifth signal, the fifth selector selects the ninth connection and does not supply the fourth signal to the second selector, even if the fifth selector receives the fourth signal.

14. The memory device of claim 4 , wherein each of the first, second and third storage areas comprises a plurality of memory cells.

15. The memory device of claim 14 , wherein each of the memory cells comprises a resistance change element capable of storing data.

16. The memory device of claim 14 , wherein each of the memory cells is one of a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM) and a resistive random access memory (ReRAM).

17. A memory device comprising:
a first storage area including a plurality of memory cells arranged in a matrix;
a second storage area;
a first sense amplifier;
a second sense amplifier;
a first selector configured to selectively switch between a first connection and a second connection, the first connection being between the first storage area and the first sense amplifier, and the second connection being between the second storage area and the first sense amplifier; and
a second selector configured to selectively switch between a third connection and a fourth connection, the third connection being between the second sense amplifier and the second storage area, and the fourth connection being between the second sense amplifier and the first storage area.

18. The memory device of claim 17 , further comprising:
a third storage area;
a third sense amplifier; and
a third selector configured to selectively switch between a fifth connection and a sixth connection, the fifth connection being between the third sense amplifier and the third storage area, and the sixth connection being between the third sense amplifier and the first storage area,
wherein the first selector is further configured to selectively switch between the first connection, the second connection, and a seventh connection, the seventh connection being between the first sense amplifier and the third

Assignees

• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C29/026

  in sense amplifiers · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title