Target capture and replay in emulation

Patent metadata

Field	Value
Publication number	US-9767237-B2
Application number	US-201514941460-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.

First claim

What is claimed is:

1. A method comprising:
performing, using an emulator that is coupled to one or more targets and that is associated with a clock for infrastructure of the emulator and a clock for a circuit design under test by the emulator, a part of an emulation process;
during the performing of the part of the emulation process:
capturing, while running the clock for the infrastructure of the emulator and the clock for the circuit design, one or more input signals that are being communicated to the emulator from the one or more targets,
communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals out of the emulator, and
storing the one or more input signals in one or more processor-readable media;

decoupling the emulator from the one or more targets;
repeating, after the decoupling, the part of the emulation process; and
during the repeating of the part of the emulation process, communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals to the emulator from the one or more processor-readable media.

2. The method recited in claim 1 , wherein the one or more processor-readable media are in a workstation.

3. The method recited in claim 1 , wherein communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals out of the emulator is performed via one or more interfaces designed for packets of data between 500 bits and 2000 bits and designed for a streaming speed between 2 and 3 gigabits per second.

4. The method recited in claim 3 , wherein communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces designed for a packet of data between 500 bits and 2000 bits and designed for a streaming speed between 2 and 3 gigabits per second.

5. The method recited in claim 1 , wherein the one or more targets comprises dynamic target.

6. The method recited in claim 1 , further comprising:
slowing, while communicating the one or more input signals out of the emulator, the clock for the circuit design based on adaptive clock management.

7. The method recited in claim 6 , further comprising:
temporarily suspending the clock for the circuit design based on the adaptive clock management.

8. The method recited in claim 1 , further comprising:
capturing, communicating out of the emulator, and storing one or more reference output signals during the performing of the part of the emulation process.

9. The method recited in claim 8 , further comprising:
comparing one or more output signals with the reference output signals during the repeating of the part of the emulation process.

10. The method recited in claim 1 , further comprising:
fetching, during the repeating of the part of the emulation process, data from the emulator while the clock for the infrastructure of the emulator and the clock for the circuit design are stopped.

11. An emulator comprising:
a clock for infrastructure of the emulator;
a clock for a circuit design under test by the emulator; and
circuitry configured to perform a method comprising:
performing, when the emulator is coupled to one or more targets, a part of an emulation process;
during the performing of the part of the emulation process:
capturing, while running the clock for the infrastructure of the emulator and the clock for the circuit design, one or more input signals that are being communicated to the emulator from the one or more targets,
communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals out of the emulator, and
causing the one or more input signals to be stored in one or more processor-readable media;

decoupling the emulator from the one or more targets;
repeating, after the decoupling, the part of the emulation; and
during the repeating of the part of the emulation process, communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals to the emulator from the one or more processor-readable media.

12. The emulator recited in claim 11 , wherein the one or more processor-readable media are in workstation in communication with the emulator.

13. The emulator recited in claim 11 , wherein communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals out of the emulator is performed via one or more interfaces to the workstation designed for a packet of data between 500 bits and 2000 bits and designed for a streaming speed between 2 and 3 gigabits per second.

14. The emulator recited in claim 13 , wherein communicating, while running the clock for the infrastructure of the emulator and the clock for the circuit design, the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces designed for a packet of data between 500 bits and 200 bits and designed for a streaming speed between 2 and 3 gigabits per second.

15. A method comprising:
performing, using an emulator that is coupled to one or more targets and that is associated with a clock for infrastructure of the emulator and a clock for a circuit design under test by the emulator, a part of an emulation process;
during the performing of the part of the emulation process:
capturing, while the clock for the infrastructure of the emulator is running and the clock for the circuit design is stopped, one or more input signals that are being communicated to the emulator from the one or more targets,
communicating, while the clock for the infrastructure of the emulator is running and the clock for the circuit design is stopped, the one or more input signals out of the emulator, and
storing the one or more input signals in one or more processor-readable media;

decoupling the emulator from the one or more targets;
repeating, after the decoupling, the part of the emulation process; and
during the repeating of the part of the emulation process, communicating, while the clock for the infrastructure of the emulator is running and the clock for the circuit design is stopped, the one or more input signals to the emulator from the one or more processor-readable media.

16. The method recited in claim 15 , wherein communicating, while the clock for the infrastructure of the emulator is running and the clock for the circuit design is stopped, the one or more input signals out of the emulator is performed via one or more interfaces designed for packets of data between 500 bits and 2000 bits and designed for a streaming speed between 2 and 3 gigabits per second.

17. The method recited in claim 16 , wherein communicating, while the clock for the infrastructure of the emulator is running and the clock for the circuit design is stopped, the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces designed for a packet of data between 500 bits and 2000 bits and designed for a streaming speed between 2 and 3 gigabits per second.

18. The method recited in claim 15 , further comprising:
slowing, while communicating the one or more input si

Assignees

• Mentor Graphics Corp

Inventors

• Suresh Krishnamurthy
• Agarwal Satish Kumar
• Gupta Sanjay
• Selvidge Charles W

Classifications

• G06F2115/10

  Processors · CPC title

• G06F2117/08

  HW-SW co-design, e.g. HW-SW partitioning · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• H04L69/28

  Timers or timing mechanisms used in protocols · CPC title

• H04L43/50

  Testing arrangements · CPC title