Hardware data structure for tracking partially ordered and reordered transactions

Patent metadata

Field	Value
Publication number	US-9767057-B2
Application number	US-201514832526-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Sep 2, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.

First claim

The invention claimed is:

1. A hardware data structure configured to track a plurality of ordered transactions in a multi-transactional hardware design comprising a slave and a plurality of masters, the slave configured to receive transaction requests from more than one of the plurality of masters, the hardware data structure comprising:
one or more counters configured to track a number of in-flight transactions in the hardware design;
a table configured to track an age of each of the in-flight transactions for the plurality of masters using the one or more counters; and
control logic configured to verify that a transaction response issued by the slave for an in-flight transaction for a particular master has been issued in a predetermined order based on the tracked age of the in-flight transaction for that master in the table.

2. The hardware data structure of claim 1 , wherein the table comprises transaction information for each master of the plurality of masters, the transaction information comprising in-flight information for each of a plurality of transactions associated with that master.

3. The hardware data structure of claim 2 , wherein the in-flight information indicates whether the transaction is in-flight and if in-flight, the age of the transaction.

4. The hardware data structure of claim 3 , wherein the in-flight information comprises a valid bit that indicates whether the transaction is in-flight and an age value that indicates the age of the transaction; or,
wherein the in-flight information comprises an age value that indicates whether the transaction is in-flight and the age of the transaction.

5. The hardware data structure of claim 3 , wherein the control logic comprises a request detection module configured to detect when a new transaction is in-flight for a specific master by monitoring one or more control signals of an input interface of the slave.

6. The hardware data structure of claim 5 , wherein the control logic further comprises a counter control module configured, in response to the request detection module detecting that a new transaction is in-flight for the specific master, to increment one of the one or more counters.

7. The hardware data structure of claim 6 , wherein the one or more counters comprises a counter for each master of the plurality of masters, each counter configured to track a number of in-flight transactions for the associated master; and the counter control module is configured, in response to the request detection module detecting that a new transaction is in-flight for the specific master, to increment the counter for the specific master.

8. The hardware data structure of claim 5 , wherein the control logic further comprises a table control module configured, in response to the request detection module detecting that a new transaction is in-flight for the specific master, to update the transaction information for the specific master so that the in-flight information for the new transaction comprises a numerical value equal to one counter of the one or more counters, the counter indicating the age of the new transaction with respect to the other in-flight transactions.

9. The hardware data structure of claim 8 , wherein the one or more counters comprises a counter for each master of the plurality of masters, each counter configured to track a number of in-flight transactions for the associated master; and the table control module is configured, in response to the request detection module detecting that a new transaction is in-flight for the specific master, to update the transaction information for the specific master so that the in-flight information for the new transaction comprises a numerical value equal to the counter for the specific master.

10. The hardware data structure of claim 8 , wherein the table control module is further configured, in response to the request detection module detecting that a new transaction is in-flight for the specific master, to update the transaction information for the specific master so that the in-flight information for the new transaction indicates the new transaction is in-flight.

11. The hardware data structure of claim 3 , wherein the control logic comprises a response detection module configured to detect when a transaction response has been issued for an in-flight transaction for a specific master by monitoring one or more control signals of an output interface of the slave.

12. The hardware data structure of claim 11 , wherein the control logic further comprises a counter control module configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to decrement one counter of the one or more counters.

13. The hardware data structure of claim 12 , wherein the one or more counters comprises a counter for each master of the plurality of masters, each counter configured to track a number of in-flight transactions for the associated master; and the counter control module is configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to decrement the counter for the specific master.

14. The hardware data structure of claim 11 , wherein the control logic further comprises a table control module configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to update the transaction information for the specific master so that the in-flight information for the transaction response indicates the transaction is not in-flight.

15. The hardware data structure of claim 14 , wherein the table control module is further configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to update the transaction information for the specific master so that the in-flight information for each in-flight transaction reflects there is one-less transaction in-flight.

16. The hardware data structure of claim 11 , wherein the control logic further comprises an error detection module configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to verify that the transaction response has been issued in a predetermined order by verifying that the in-flight transaction is the oldest in-flight transaction for the specific master based on the transaction information for the specific master.

17. The hardware data structure of claim 11 , wherein the control logic further comprises an error detection module configured, in response to the response detection module detecting that a transaction response has been issued for an in-flight transaction for a specific master, to verify that the transaction response has been issued in a predetermined order using one or more assertions written in an assertion-based language.

18. The hardware data structure of claim 2 , wherein each transaction comprises a transaction ID and the in-flight information for a particular transaction is identified by the transaction ID.

19. A method of tracking a plurality of transactions in a multi-transactional hardware design comprising a slave and a plurality of masters, the slave configured to receive transaction requests from more than one of the plurality of masters, the method comprising:
tracking a number of in-flight transaction

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F11/28 Primary

  by checking the correct order of processing (G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19) · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F11/30

  Monitoring · CPC title