Method for controlling transaction exchanges between two integrated circuits

Patent metadata

Field	Value
Publication number	US-9767056-B2
Application number	US-201214130646-A
Country	US
Kind code	B2
Filing date	Jul 6, 2012
Priority date	Jul 6, 2011
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed.

First claim

The invention claimed is:

1. A method for controlling transaction exchanges between two integrated circuits in a system comprising:
the two integrated circuits,
a power supply for supplying power to a link between the two integrated circuits, thereby enabling transaction exchanges between both integrated circuits, and
a controller controlling the integrated circuits and the power supply, the method comprising the steps of:
receiving an order at the controller, wherein the order requires the link to be closed; and
in response to the order, first stopping initiation of new transaction requests and subsequently closing the link after all pending transactions of both of the two integrated circuits have been executed by:
sending an instruction from the controller to each of the two integrated circuits, wherein the instruction causes each of the two integrated circuits to stop initiating new transaction requests;
for each one of the two integrated circuits, detecting that the one of the two integrated circuits has stopped initiating new transactions, and in response to detecting that the one of the two integrated circuits has stopped initiating new transactions, detecting when all pending transactions initiated by the one of the two integrated circuits have been executed; and
closing the link in response to detecting that all pending transactions of both of the two integrated circuits have been executed.

2. The method of claim 1 , wherein the order is an order to power down the link.

3. The method of claim 1 , wherein the link operates in accordance with a circuit-to-circuit serial interface protocol.

4. The method of claim 1 , wherein the link operates in accordance with a Mobile Industry Processor Interface (MIPI) Low Latency Interface.

5. The method of claim 1 , wherein at least one of the integrated circuits has an interconnect to which power is supplied by an interconnect power supply, which is only used in the transaction exchanges between the two integrated circuits and wherein closing the link comprises lowering the power supplied by the interconnect power supply in response to detecting that all pending transactions of both of the two integrated circuits have been executed.

6. The method of claim 5 , wherein lowering the power supplied by the interconnect power supply comprises powering down the interconnect power supply.

7. The method of claim 1 , wherein one of the integrated circuits is a master integrated circuit and the other one of the integrated circuits is a slave integrated circuit.

8. The method of claim 1 , wherein the system comprises at least one monitor able to provide a signal representative of a number of pending transactions, and wherein detecting when all pending transactions initiated by the one of the two integrated circuits have been executed comprises sending the signal from the monitor of the one of the two integrated circuits to the controller when the number of pending transactions reaches zero.

9. A system comprising:
two integrated circuits;
a power supply configured to supply power to a link between the two integrated circuits, thereby enabling transaction exchanges between both of the two integrated circuits;
a controller configured to control the two integrated circuits and the power supply;
wherein the controller is configured to respond to an order by:
in response to the order, first stopping initiation of new transaction requests and subsequently closing the link after all pending transactions of both of the two integrated circuits have been executed by:
sending an instruction to each of the two integrated circuits, wherein the instruction causes each of the two integrated circuits to stop initiating new transaction requests;
causing each one of the two integrated circuits to detect that the one of the two integrated circuits has stopped initiating new transactions, and in response to detecting that the one of the two integrated circuits has stopped initiating new transactions, detect when all pending transactions initiated by the one of the two integrated circuits have been executed; and
closing the link in response to detecting that all pending transactions of both of the two integrated circuits have been executed, wherein the order is an order that requires the link to be closed.

10. The system according to claim 9 , wherein the order that requires the link to be closed is an order to power down the link, and wherein the controller is configured to stop the power supply of the link in response to detecting that all pending transactions of both of the two integrated circuits have been executed.

11. The method of claim 1 , comprising:
at least one component on at least one of the two integrated circuits performing:
receiving, from the controller, the instruction that causes each of the two integrated circuits to stop initiating new transaction requests;
in response to the received instruction, continuing to initiate new transaction requests only until the at least one component has transitioned into a predefined safe state; and
in response to the at least one component having transitioned into the predefined safe state, notifying the controller that the at least one component has stopped initiating new transactions.

12. The system of claim 9 , comprising:
at least one component on at least one of the two integrated circuits configured to perform:
receiving, from the controller, the instruction that causes each of the two integrated circuits to stop initiating new transaction requests;
in response to the received instruction, continuing to initiate new transaction requests only until the at least one component has transitioned into a predefined safe state; and
in response to the at least one component having transitioned into the predefined safe state, notifying the controller that the at least one component has stopped initiating new transactions.

13. The method of claim 1 , wherein the order is an order to lower the power supplied to the link.

14. The system of claim 9 , wherein the order is an order to lower the power supplied to the link.

15. The method of claim 8 , wherein the monitor comprises an up/down counter configured to count in one of two directions in response to initiation of a transaction request, and to count in another of the two directions in response to receipt of a transaction response.

16. The system of claim 9 , comprising at least one monitor configured to generate representation of a number of pending transactions and to send a signal to the controller when the number of pending transactions reaches zero,
wherein the monitor comprises an up/down counter configured to count in one of two directions in response to initiation of a transaction request, and to count in another of the two directions in response to receipt of a transaction response.

17. The method of claim 1 , comprising using an interrupt mechanism to inform the controller that all pending transactions initiated by the one of the two integrated circuits have been executed.

18. The system of claim 9 , comprising an interrupt mechanism configured to inform the controller that all pending transactions initiated by the one of the two integrated circuits have been executed.

19. A non-transitory processor readable storage medium having stored therein instructions that, when executed by a processor, cause the processor to perform a method for controlling transaction exchanges between two integrated circuits in a system comprising:
the two integrated circuits,
a power supply for supplying p

Assignees

• Balakrishnan Bipin
• Goulahsen Abdelaziz
• ERICSSON TELEFON AB L M (publ)

Inventors

• Balakrishnan Bipin
• Goulahsen Abdelaziz

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3253

  Power saving in bus · CPC title