Initializing I/O devices

US9767048B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9767048-B2
Application numberUS-201514862221-A
CountryUS
Kind codeB2
Filing dateSep 23, 2015
Priority dateOct 7, 2014
Publication dateSep 19, 2017
Grant dateSep 19, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.

First claim

Opening claim text (preview).

What is claimed is: 1. A data processing system comprising: a processor nest coupled to a processor core, the processor nest comprising memory subsystem and a bus controller, the processor nest being communicatively coupled to an input/output (I/O) bus by the bus controller and providing a mainline I/O path of the processor core to the I/O bus; and a service interface controller, separate from the mainline I/O path of the processor nest, and communicatively coupled to use the bus controller, allowing the service interface controller access to the I/O bus separate from the mainline I/O path of the processor core to the I/O bus, wherein the system further comprises: storage communicatively coupled to the service interface controller for storing commands for access by the bus controller and associated command data and resulting status data, the storage being associated with the bus controller, and the commands being associated with the service interface controller; and the service interface controller being configured, in response to received service commands, to read and write the storage, to execute a command specified in the storage, to retrieve the result of the command, and to store the result in the storage. 2. The data processing system of claim 1 , wherein the service interface controller is connected directly to the bus controller of the mainline I/O path for the processor core. 3. The data processing system of claim 1 , wherein the service interface controller is communicatively coupled to an I/O interface of the bus controller, the I/O interface being coupled to the I/O bus. 4. The data processing system of claim 1 , wherein an interface arbiter is provided to interleave I/O bus communication of the mainline I/O path for the processor core to the I/O bus and the service interface controller. 5. The data processing system of claim 4 , wherein the interface arbiter is part of the bus controller and comprises at least a request arbiter and/or a multiplexer. 6. The data processing system of claim 1 , wherein the storage comprises at least one of a command register, a data register, or a status register for use by the service interface controller. 7. The data processing system of claim 1 , wherein the storage is part of the bus controller. 8. A method for communicating to an input/output bus of a data processing system, the method comprising: storing in storage commands for a bus controller and associated command data and resulting status data in a storage, the storage being communicatively coupled to the bus controller, and the commands being associated with a service interface controller, the bus controller being part of a processor nest associated with a processor core, the processor nest further comprising a memory subsystem and providing a mainline I/O path for the processor core to an I/O bus, the service interface controller being separate from the mainline I/O path, and communicatively coupled to use the bus controller, allowing the service interface controller to access to the I/O bus separate from the mainline I/O path of the processor core to the I/O bus access to the I/O bus; reading and writing the storage by the service interface controller, in response to a received service command; executing a command specified in the storage; retrieving the result of the command; and storing the result of the command in the storage. 9. The method of claim 8 , wherein communication between the service interface controller and the bus controller is performed without the processor core running. 10. The method of claim 8 , wherein commands from the service interface controller are interleaved with commands of the mainline I/O path using an interface arbiter of the bus controller. 11. The method of claim 8 , wherein commands from the service interface controller are tagged to facilitate interleaving with commands of the mainline I/O path. 12. The method of claim 8 , wherein the service interface controller is configured to read/write all registers of the storage accessible by the service interface controller. 13. A computer program product for facilitating communicating to an input/output (I/O) bus of a data processing system, the computer program product comprising: a non-transitory computer readable storage medium storing a computer readable program, wherein the computer readable program when executed by a processor causes the processor to perform a method of communicating to the input/output bus of the data processing system, the data processing system comprising a processor nest communicatively coupled to a processor core, the processor nest comprising a memory subsystem and a bus controller for the processor core, the processor nest further being communicatively coupled to the I/O bus by the bus controller and providing a mainline I/O path for the processor core to the I/O bus, the data processing system further comprising a service interface controller communicatively coupled to storage for storing commands for access by the bus controller, the service interface controller being communicatively coupled to use the bus controller, allowing the service interface controller access to the I/O bus separate from the mainline I/O path for the processor core to the I/O bus, the method comprising: storing commands for the bus controller and associated command data and resulting status data in storage, the storage being communicatively coupled to the processor nest and the bus controller; reading and writing the storage by the service interface controller, in response to a received service command; executing the command specified in the storage; retrieving the result of the command; and storing the result of the command in the storage. 14. The computer program product of claim 13 , wherein communication between the service interface controller and the bus controller is performed without the processor core running. 15. The computer program product of claim 13 , wherein commands from the service interface controller are interleaved with commands of the mainline I/O path within the bus controller. 16. The computer program product of claim 13 , wherein commands from the service interface controller are tagged to facilitate interleaving with commands of the mainline I/O path. 17. The computer program product of claim 13 , wherein the service interface controller is configured to read/write all registers of the storage accessible by the service interface controller.

Assignees

Inventors

Classifications

  • Electrical coupling · CPC title

  • G06F13/102Primary

    where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

  • for access to input/output bus · CPC title

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What does patent US9767048B2 cover?
A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the pr…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F13/102. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).