Apparatus, system, and method for persistent user-level thread

Patent metadata

Field	Value
Publication number	US-9766891-B2
Application number	US-201615166469-A
Country	US
Kind code	B2
Filing date	May 27, 2016
Priority date	Sep 30, 2005
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

First claim

What is claimed is:

1. A processor comprising:
a first plurality of cores to execute an operating system; and
a second plurality of cores, wherein the second plurality of cores are to be sequestered from and invisible to the operating system, wherein at least one of the first plurality of cores is to execute an application that is to schedule work, independently of the operating system, to at least one of the second plurality of cores, wherein in response to a page fault encountered by the at least one of the second plurality of cores, one or more of the first plurality of cores are to execute the operating system to handle the page fault.

2. The processor of claim 1 , wherein the at least one of the first plurality of cores and the at least one of the second plurality of cores are to execute in a shared virtual address space.

3. The processor of claim 1 , wherein the first core of the first plurality of cores comprises at least one operating system-visible sequencer to execute instructions scheduled by the operating system.

4. The processor of claim 3 , wherein a second core of the second plurality of cores comprises at least one operating system-sequestered sequencer for which the operating system does not schedule instructions.

5. The processor of claim 4 , wherein the at least one operating system-visible sequencer is to create a persistent user-level thread of the application to run on the at least one operating system-sequestered sequencer.

6. The processor of claim 5 , wherein the persistent user-level thread is to continue execution, irrespective of context switch activities of an operating system-scheduled thread of the application executed on the at least one operating system-visible sequencer.

7. The processor of claim 5 , wherein the processor is to suspend execution of the persistent user-level thread in response to the page fault, and communicate to a second operating system-visible sequencer a control transfer instruction for execution at a privileged level.

8. The processor of claim 7 , further comprising a sequencer manager to cause a service thread to execute on the at least one operating system-visible sequencer to handle the page fault for the suspended persistent user-level thread.

9. The processor of claim 8 , wherein the sequencer manager is to:
cause the service thread to pick up a state of the persistent user-level thread;
provide a proxy execution to the persistent user-level thread; and
return a post execution state to the persistent user-level thread to enable the persistent user-level thread to resume running from the post execution state.

10. The processor of claim 1 , wherein the first plurality of cores is asymmetric to the second plurality of cores.

11. The processor of claim 1 , wherein the processor comprises a digital signal processor (DSP).

12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
creating a first user-level thread of an application to run on a first core of a plurality of operating system-sequestered cores of a processor by an operating system-scheduled thread running on a second core of a plurality of operating system-visible cores of the processor, wherein the first user-level thread continues execution when the operating system-scheduled thread is context switched;
encountering a page fault in the first user-level thread;
handling the page fault on one or more of the plurality of operating system-visible cores; and
thereafter continuing execution of the first user-level thread on the first core.

13. The non-transitory machine-readable medium of claim 12 , wherein the operating system-scheduled thread and the first user-level thread share a common virtual address space.

14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises causing a service thread running on another core of the plurality of operating system-visible cores to imitate the first user-level thread to provide an operating system service to the first user-level thread, including accessing an execution state of the first user-level thread.

15. The non-transitory machine-readable medium of claim 14 , wherein the method further comprises:
accessing the execution state of the first user-level thread through the common virtual address space;
providing a proxy execution to the first user-level thread; and
returning a post execution state to the first user-level thread.

16. The non-transitory machine-readable medium of claim 15 , wherein the method further comprises resuming running of the first user-level thread from the post execution state.

17. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises processing instructions at a first rate in the first core and at a second rate in the second core.

18. A multi-core processor comprising:
a first plurality of cores that are visible to an operating system;
a second plurality of cores that are sequestered from the operating system; and
a controller to create a first user-level thread to run on a first core of the second plurality of cores, communicate a control transfer instruction to a core of the first plurality of cores, and execute the control transfer instruction at a privileged level, wherein the first user-level thread is to continue execution when an operating system-scheduled thread in execution on another core of the first plurality of cores is context switched.

19. The multi-core processor of claim 18 , wherein the first user-level thread is to be suspended when a page fault is encountered, and a service thread to run on one or more of the first plurality of cores is to imitate the suspended first user-level thread to handle the page fault.

20. The multi-core processor of claim 19 , wherein the multi-core processor is to:
cause the service thread to access an execution state of the first user-level thread through a shared virtual address space;
provide a proxy execution to the first user-level thread; and
return a post execution state to the first user-level thread to enable the first user-level thread to resume from the post execution state.

Assignees

• Intel Corp

Inventors

• Chinya Gautham
• Wang Hong
• Sethi Prashant
• Kaushik Shivnandan
• Bigbee Bryant
• Shen John
• Hankins Richard
• Zou Xiang
• Patel Baiju V
• Brandt Jason W
• Aggarwal Anil
• Reid John L

Classifications

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/3009 Primary

  Thread control instructions · CPC title