Multi-register gather instruction

Patent metadata

Field	Value
Publication number	US-9766887-B2
Application number	US-201113995437-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand that identifies content that indicates multiple vector registers, a first set of indexes of each of the vector registers that each identifies a source data element, and a second set of indexes of the destination vector register for each identified source element. The instruction is decoded and executed, causing, for each of the first set of indexes of each of the vector registers, the source data element that corresponds to that index of that vector register to be stored in a set of destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.

First claim

What is claimed is:

1. A comprising:
fetching a single instruction, wherein the single instruction includes a destination operand that specifies a destination vector register and a source operand that identifies content that indicates:
a plurality of first vector registers,
a first set of two or more indexes of each of the plurality of first vector registers, wherein each of the first set of indexes identifies a source data element in its corresponding one of the first vector registers, and
a second set of two or more indexes of the destination vector register for each identified source data element;

decoding the fetched single instruction; and
executing the decoded single instruction which causes, for each of the first set of indicated indexes of each of the plurality of first vector registers, the source data element that corresponds to that indicated index of that one of the first vector registers to be stored in a set of one or more destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.

2. The method of claim 1 , wherein the source operand specifies a second vector register whose content includes a plurality of data elements that specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

3. The method of claim 2 , wherein the contents of each of the plurality of data elements in the second vector register further indicates whether a source data element of one of the plurality of first vector registers is to be stored in a destination data element of the destination vector register.

4. The method of claim 2 , wherein the second set of indexes of the destination vector register for each identified source data element is indicated through corresponding indexes of the second vector register.

5. The method of claim 2 , wherein the source vector register is a 512-bit register.

6. The method of claim 1 , wherein the source operand specifies a location in memory whose contents specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

7. The method of claim 1 , wherein the destination vector register is a 512-bit register.

8. A processor core, comprising:
a hardware decode unit to decode a single instruction, wherein the single instruction includes a destination operand that specifies a destination vector register and a source operand that identifies content that indicates:
a plurality of first vector registers,
a first set of two or more indexes of each of the plurality of first vector registers, wherein each of the first set of indexes identifies a source data element in its corresponding one of the first vector registers, and
a second set of two or more indexes of the destination vector register for each identified source data element;

an execution engine unit to execute the decoded single instruction which causes, for each of the for each of the first set of indicated indexes of each of the plurality of first vector registers, the source data element that corresponds to that indicated index of that one of the first vector registers to be stored in a set of one or more destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.

9. The processor core of claim 8 , wherein the source operand specifies a second vector register whose content includes a plurality of data elements that specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

10. The processor core of claim 9 , wherein the contents of each of the plurality of data elements in the second vector register further indicates whether a source data element of one of the plurality of first vector registers is to be stored in a destination data element of the destination vector register.

11. The processor core of claim 9 , wherein the second set of indexes of the destination vector register for each identified source data element is indicated through corresponding indexes of the second vector register.

12. The processor core of claim 9 , wherein the source vector register is a 512-bit register.

13. The processor core of claim 8 , wherein the source operand specifies a location in memory whose contents specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

14. The processor core of claim 8 , wherein the destination vector register is a 512-bit register.

15. An article of manufacture, comprising:
a non-transitory tangible machine-readable storage medium having stored thereon a single instruction, wherein the single instruction includes a destination operand that specifies a destination vector register and a source operand that identifies content that indicates:
a plurality of first vector registers,
a first set of two or more indexes of each of the plurality of first vector registers, wherein each of the first set of indexes identifies a source data element in its corresponding one of the first vector registers, and
a second set of two or more indexes of the destination vector register for each identified source data element; and
wherein the single instruction includes an opcode, which instructs a machine to execute the instruction that causes, for each of the first set of indicated indexes of each of the plurality of first vector registers, the source data element that corresponds to that indicated index of that one of the first vector registers to be stored in a set of one or more destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.

16. The article of manufacture of claim 15 , wherein the source operand specifies a second vector register whose content includes a plurality of data elements that specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

17. The article of manufacture of claim 16 , wherein the contents of each of the plurality of data elements in the second vector register further indicates whether a source data element of one of the plurality of first vector registers is to be stored in a destination data element of the destination vector register.

18. The article of manufacture of claim 16 , wherein the second set of indexes of the destination vector register for each identified source data element is indicated through corresponding indexes of the second vector register.

19. The article of manufacture of claim 16 , wherein the source vector register is a 512-bit register.

20. The article of manufacture of claim 15 , wherein the source operand specifies a location in memory whose contents specify the plurality of first vector registers and the first set of indexes of the plurality of first vector registers.

21. The article of manufacture of claim 15 , wherein the destination vector register is a 512-bit register.

Assignees

• Jha Ashish
• Intel Corp

Inventors

• Jha Ashish

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30038

  using a mask · CPC title