Stripe mapping in memory

Patent metadata

Field	Value
Publication number	US-9766837-B2
Application number	US-201514735838-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 10, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

First claim

What is claimed is:

1. A method for stripe mapping, comprising:
writing data in a number of stripes across a storage volume of a plurality of memory devices according to a first stripe map;
wherein each of the number of stripes includes a number of elements;
wherein the first stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes;
storing a second stripe map, wherein the second stripe map is an inverse stripe map of the first stripe map;
using the second stripe map to perform a redundant array of independent disks (RAID) read error recovery operation to identify one or more stripes including one or more bad elements; and
updating the one or more stripes including the one or more bad elements in the first stripe map.

2. The method of claim 1 , wherein the method includes creating the first stripe map by associating each of the number of stripe indexes with a portion of the elements in the plurality of memory devices.

3. The method of claim 1 , wherein the method includes creating the first stripe map by associating each of the number of stripes with a parity element identifier.

4. The method of claim 1 , wherein the method includes creating the first stripe map by selecting the elements to include in the number of stripes based on a bit error rate associated with the elements.

5. The method of claim 1 , wherein the method includes creating the first stripe map by selecting the pages to include in the number of stripes based on a location of the pages within the plurality of memory devices.

6. The method of claim 1 , wherein writing data in the number of stripes includes splitting the data into the number of elements and writing the number of elements to the plurality of memory devices.

7. The method of claim 6 , wherein writing the number of elements to the plurality of memory devices includes writing at least one element to each of the plurality of memory devices.

8. The method of claim 6 , wherein writing the number of elements to the plurality of memory devices includes writing at least one element to each of a subset of the plurality of memory devices.

9. The method of claim 8 , wherein writing at least one element to each of a subset of the plurality of memory devices includes writing a respective page of the write data to each of a subset of the plurality of memory devices.

10. A method for stripe mapping, comprising:
storing a first stripe map that includes element identifier information for each element associated with a number of stripes in memory, wherein each element associated with the number of stripes is included in a particular strip based a likelihood of a read error occurring in a particular element;
writing data to the number of stripes in the memory, wherein the data is striped across the memory based on the element identifier information of the stripe maps;
storing a second stripe map, wherein the second stripe map is an inverse stripe map of the first stripe map;
using the second stripe map to perform a read error recovery operation to identify one or more stripes including one or more bad elements; and
updating the one or more stripes including the one or more bad elements in the first stripe map.

11. The method of claim 10 , wherein storing the first stripe map includes providing a physical address for each element associated with the number of stripes.

12. The method of claim 11 , wherein the physical address for each element associated with the number of stripes includes channel, device, block, and page information.

13. The method of claim 10 , wherein storing the first stripe map includes providing a particular stripe index for each of the number of stripes.

14. The method of claim 10 , wherein the first stripe map includes pages with varied bit error rates included in each of the number of stripes.

15. The method of claim 10 , wherein the first stripe map includes pages selected based on physical location of the pages on the memory device.

16. The method of claim 10 , wherein the method includes storing the second stripe map, wherein the second stripe map is indexed by element and identifies each stripe that is associated with each particular element.

17. The method of claim 10 , wherein the method includes updating the first stripe map by replacing element identifiers of bad elements with element identifiers of different element.

18. The method claim 10 , wherein the first stripe map includes a number of elements associated with a particular stripe, wherein the number of elements is variable.

19. The method claim 10 , wherein the first stripe map includes a parity element identifier included in each of the number of stripes.

20. A method for stripe mapping, comprising:
storing a first stripe map, wherein the first stripe map is indexed by element and identifies each stripe that is associated with each particular element of a number of elements in a plurality of memory devices; and
performing a read error recovery operation by locating a bad element in the stripe map using a second stripe map, that is the inverse stripe map of the first stripe map, to perform the read error recovery operation and updating each of the number of stripes associated with the bad element in the first stripe map.

21. The method of claim 20 , wherein updating each of the number of stripes includes replacing the element page with a new element.

22. The method of claim 20 , wherein the method includes performing the read error recovery operation in response to an error correction code (ECC) operation failure.

23. The method of claim 20 , wherein creating the first stripe map includes identifying each of the particular elements with a page identifier.

24. The method of claim 20 , wherein the method includes updating the first stripe map by removing element identifiers of bad elements from the stripe map.

25. An apparatus, comprising:
a number of memory devices;
a controller coupled to the number of memory devices and configured to:
store a first stripe map comprising element identifiers for each element of a number of stripes in the number of memory devices, wherein the first stripe map defines particular elements of particular stripes;
write data to the number of memory devices, wherein the data is written to elements of the number of stripes defined by the first stripe map;
store a second stripe map comprising an inverse stripe map of the first stripe map, wherein the second stripe map is used to perform a read error recovery operation to identify one or more stripes including one or more bad elements; and
update the one or more stripes including the one or more bad elements in the first stripe map.

26. The apparatus of claim 25 , wherein the element identifiers for each element includes channel, device, block, and page information.

27. The apparatus of claim 25 , wherein the particular elements of particular stripes include varied bit error rates.

28. The apparatus of claim 25 , wherein the particular elements of particular stripes are selected based on physical locations in the number of memory devices.

29. The apparatus of claim 25 , wherein the physical locations are selected based on bit error rates associated with the physical locations.

30. The apparatus of claim 25 ,

Assignees

• Micron Technology Inc

Inventors

• Mcglaughlin Edward
• Jeddeloh Joseph M

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/064

  Management of blocks · CPC title