Apparatus for data retention and supply noise mitigation using clamps

Patent metadata

Field	Value
Publication number	US-9766827-B1
Application number	US-201615151402-A
Country	US
Kind code	B1
Filing date	May 10, 2016
Priority date	May 10, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

First claim

We claim:

1. An apparatus comprising:
a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and
a second power gate transistor coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic has multiple modes including:
weakly turn on the second power gate transistor,
diode-connect the second power gate transistor,
substantially turn on the second power gate transistor, and
turn off the second power gate transistor.

2. The apparatus of claim 1 , wherein the second logic comprises transistors which are collectively smaller in size than the size of the second power gate transistor.

3. The apparatus of claim 1 , wherein the second logic is operable to weakly turn on the second power gate transistor such that at least two diodes are formed between the ungated power supply node and the gated power supply node.

4. The apparatus of claim 1 , wherein the second logic is operable to substantially turn on the second power gate transistor during a normal active mode, and wherein the second logic is operable to fully turn off the second power gate transistor during a destructive sleep mode.

5. The apparatus of claim 1 , wherein the second logic is operable to cause the second power gate transistor to electrically form a diode between the ungated power supply node and the gated power supply node.

6. The apparatus of claim 1 , wherein the second logic comprises a first p-type transistor coupled to the gate terminal of the second power gate transistor and the ungated power supply node.

7. The apparatus of claim 6 , wherein the second logic comprises a second p-type transistor coupled in series with the first p-type transistor, and coupled to the gate terminal of the second power gate transistor and the gated power supply node.

8. The apparatus of claim 7 , wherein the second logic comprises a third p-type-transistor coupled to a gate terminal of the first p-type transistor and the gate terminal of the second power gate transistor.

9. The apparatus of claim 8 , wherein the second logic comprises a fourth p-type transistor coupled to a gate terminal of the second p-type transistor and the gated power supply node.

10. The apparatus of claim 1 , wherein the second logic comprises a first n-type transistor coupled to the gate terminal of the second power gate transistor and a ground node.

11. The apparatus of claim 1 , wherein the first logic comprises:
a first p-type transistor coupled to the ungated power supply node and the gate terminal of the first power gate transistor; and
a first n-type transistor coupled in series with the first p-type transistor, the first n-type transistor coupled to the gate terminal of the first power gate and a ground node.

12. An apparatus comprising:
a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and
a second power gate transistor coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic includes:
a first p-type transistor coupled to the gate terminal of the second power gate transistor and the ungated power supply node;
a second p-type transistor coupled in series with the first p-type transistor, and coupled to the gate terminal of the second power gate transistor and the gated power supply node;
a third p-type-transistor coupled to a gate terminal of the first p-type transistor and the gate terminal of the second power gate transistor; and
a fourth p-type transistor coupled to a gate terminal of the second p-type transistor and the gated power supply node.

13. The apparatus of claim 12 , wherein the first, second, third, and fourth transistors are collectively smaller in size than the size of the second power gate transistor.

14. The apparatus of claim 12 , wherein the second logic is operable to weakly turn on the second power gate transistor such that at least two diodes are formed between the ungated power supply node and the gated power supply node.

15. The apparatus of claim 12 , wherein the second logic is operable to substantially turn on the second power gate transistor during a normal active mode, and wherein the second logic is operable to fully turn off the second power gate during a destructive sleep mode.

16. The apparatus of claim 12 , wherein the second logic is operable to cause the second power gate transistor to electrically form a diode between the ungated power supply node and the gated power supply node.

17. The apparatus of claim 12 , wherein the first logic comprises:
a first p-type transistor coupled to the ungated power supply node and the gate terminal of the first power gate transistor; and
a first n-type transistor coupled in series with the first p-type transistor, the first n-type transistor coupled to the gate terminal of the first power gate transistor and a ground node.

18. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a first logic block;
a second logic block;
an ungated power supply node extending along the first and second logic blocks;
a first power gate transistor coupled to the ungated power supply node common to the first and second logic blocks and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and
a second power gate transistor coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to:
weakly turn on the second power gate transistor,
substantially turn on the second power gate transistor,
turn off the second power gate transistor, and
configuring the second power gate transistor as a diode; and

a wireless interface for allowing the processor to communicate with another device.

19. The system of claim 18 , wherein the processor is a graphics processor, and wherein the at least one of the first and second logic blocks is an execution unit.

20. The system of claim 18 , wherein the processor includes a voltage regulator to provide power supply to the ungated power supply node.

Assignees

• Intel Corp

Inventors

• Meinerzhagen Pascal A
• Kim Stephen T
• Thaploo Anupama A
• Khellah Muhammad M

Classifications

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title