Pixel unit and array substrate

Patent metadata

Field	Value
Publication number	US-9766510-B2
Application number	US-201514907820-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Sep 30, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

The present invention provides a pixel unit and an array substrate. The pixel electrode includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product and also simplifying the structure of the pixel electrode and making the manufacturing process simple, and facilitating the production of large-size wide-angle display products. The array substrate of the present invention is composed, in the horizontal direction, of multiple pixel units. The pixel units each include a pixel electrode that includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product, and the pixel electrode has a simple structure to simplify the manufacturing process and facilitate the production of large-size wide-angle display products.

First claim

What is claimed is:

1. A pixel unit, comprising a pixel zone that comprises two long edges opposite to each other and two short edges respectively connected to the two long edges, a pixel electrode arranged at a center of the pixel zone, a data line arranged alone one of the long edges of the pixel zone, and a gate line perpendicular to the data line and extending through the pixel electrode;
the pixel electrode comprising a connection section located at a center thereof and four branch sections extending from the connection section to a perimeter of the pixel zone, the four branch sections being symmetric, in a top-bottom direction and a left-right direction, with respect to straight lines that extend through the connection section and are respectively parallel to the long edges and the short edges of the pixel zone, the branch sections each starting from the connection section, then extending in a direction, which is parallel to the long edges of the pixel zone, toward the short edges of the pixel zone, and further extending toward the long edges of the pixel zone at a location close to the short edges of the pixel zone, wherein each of the branch sections comprises an electrode strip that is of a closed form having a starting point and an ending point both coincident with the connection section.

2. The pixel unit as claimed in claim 1 , wherein the electrode strip comprises a smooth curve.

3. The pixel unit as claimed in claim 1 , wherein the electrode strip comprises a plurality of linear segments, the plurality of linear segments comprising a first slope segment starting from the connection section, a first vertical segment connected to a distal end of the first slope segment and extending toward one of the short edges of the pixel zone, a second slope segment connected to a distal end of the first vertical segment and extending toward one of the long edges of the pixel zone, a first horizontal segment connected to a distal end of the second slope segment and parallel to the short edges of the pixel zone, a third slope segment connected to a distal end of the first horizontal segment and parallel to the second slope segment, a second vertical segment connected to a distal end of the third slope segment and parallel to the first vertical segment, and a fourth slope segment connecting the second vertical segment to the connection section.

4. An array substrate, comprising, in a vertical direction, a backing plate, a light-shielding layer arranged on the backing plate, a buffer layer arranged on the light-shielding layer and the backing plate, a poly-silicon layer arranged on the buffer layer, a gate insulation layer arranged on the poly-silicon layer, a gate electrode and a gate line arranged on the gate insulation layer, an inter-layer insulation layer arranged on the gate electrode and the gate insulation layer, a source electrode, a drain electrode, and a data line arranged on the inter-layer insulation layer, a planarization layer arranged on the source electrode, the drain electrode, and the inter-layer insulation layer, a common electrode arranged on the planarization layer, a passivation layer arranged on the common electrode, and a pixel electrode arranged on the passivation layer;
the array substrate being divided, in a horizontal direction, into multiple pixel zones, each of the pixel zones comprising a pixel electrode, the pixel zone comprising two long edges that are opposite to each other and two short edges respectively connected to the two long edges, the data line being arranged, in the horizontal direction, along one of the long edges of the pixel zone, the gate line being arranged, in the horizontal direction, to be perpendicular to the data line and extending through the pixel electrode;
the pixel electrode comprising a connection section located at a center thereof and four branch sections extending from the connection section to a perimeter of the pixel zone, the four branch sections being symmetric, in a top-bottom direction and a left-right direction, with respect to straight lines that extend through the connection section and are respectively parallel to the long edges and the short edges of the pixel zone, the branch sections each starting from the connection section, then extending in a direction, which is parallel to the long edges of the pixel zone, toward the short edges of the pixel zone, and further extending toward the long edges of the pixel zone at a location close to the short edges of the pixel zone, wherein each of the branch sections comprises an electrode strip that is of a closed form having a starting point and an ending point both coincident with the connection section.

5. The array substrate as claimed in claim 4 , wherein the electrode strip comprises a smooth curve.

6. The array substrate as claimed in claim 4 , wherein the electrode strip comprises a plurality of linear segments, the plurality of linear segments comprising a first slope segment starting from the connection section, a first vertical segment connected to a distal end of the first slope segment and extending toward one of the short edges of the pixel zone, a second slope segment connected to a distal end of the first vertical segment and extending toward one of the long edges of the pixel zone, a first horizontal segment connected to a distal end of the second slope segment and parallel to the short edges of the pixel zone, a third slope segment connected to a distal end of the first horizontal segment and parallel to the second slope segment, a second vertical segment connected to a distal end of the third slope segment and parallel to the first vertical segment, and a fourth slope segment connecting the second vertical segment to the connection section.

7. The array substrate as claimed in claim 4 , wherein the inter-layer insulation layer and the gate insulation layer comprise first vias formed therein to respectively correspond to two ends of the poly-silicon layer and the source electrode and the drain electrode are respectively connected, through the first vias, to the poly-silicon layer.

8. The array substrate as claimed in claim 4 , wherein the planarization layer comprises a second via formed therein to correspond to the drain electrode, the connection section of the pixel electrode being arranged in the second via and is connected to the drain electrode that is located under the second via.

9. The array substrate as claimed in claim 4 , wherein the array substrate is applicable to a fringe field switching (FFS) liquid crystal display panel.

10. The array substrate as claimed in claim 4 , wherein the common electrode and the pixel electrode are each formed of a material comprising indium tin oxide (ITO).

11. An array substrate, comprising, in a vertical direction, a backing plate, a light-shielding layer arranged on the backing plate, a buffer layer arranged on the light-shielding layer and the backing plate, a poly-silicon layer arranged on the buffer layer, a gate insulation layer arranged on the poly-silicon layer, a gate electrode and a gate line arranged on the gate insulation layer, an inter-layer insulation layer arranged on the gate electrode and the gate insulation layer, a source electrode, a drain electrode, and a data line arranged on the inter-layer insulation layer, a planarization layer arranged on the source electrode, the drain electrode, and the inter-layer insulation layer, a common electrode arranged on the planarization layer, a passivation layer arranged on the common electrode, and a pixel electrode arranged on the passivation layer;
the array substrate being divided, in a horizontal direction, into multiple pixel zones, each of the pixel zones comprising a pixel electrode, the

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Meng Lin

Classifications

• H01L27/124

  Electricity · mapped topic

• G02F2001/134372

  Physics · mapped topic

• G02F2201/123

  pixel · CPC title

• G02F2201/121

  common or background · CPC title

• H01L29/78675

  Electricity · mapped topic