Configurable multi-rate format for communication system for silicon photonics

US9762984B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9762984-B2
Application numberUS-201715403529-A
CountryUS
Kind codeB2
Filing dateJan 11, 2017
Priority dateJul 11, 2013
Publication dateSep 12, 2017
Grant dateSep 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: a substrate member; a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol; an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block configured to convert N first data streams into M second data streams, each of the first data streams having a first predefined data rate at a first clock rate and each of the second data streams having a second predefined data rate at a second clock rate; a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block, wherein the signal processing block executes a wavelength divisional scheme to produce a data packet modulated with a multi-channel-multi-bitrate; a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking; a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in either an amplitude modulation format or a combination of phase/amplitude modulation format or a phase modulation format; a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using a loop back signal from an optical tap coupler, and configured to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface. 2. The device of claim 1 further comprising a broad band source in optical communication with the receiver module. 3. The device of claim 1 wherein the TIA block is coupled to the silicon photonics device using the loop back signal through an isolation switch. 4. The device of claim 1 wherein the driver module is selected from a current drive or a voltage driver. 5. The device of claim 1 wherein the driver module is a differential driver. 6. The device of claim 1 wherein the amplified modulation format is selected from NRZ format or PAM format. 7. The device of claim 1 wherein the phase modulation format is selected from BPSK or nPSK. 8. The device of claim 1 wherein the phase/amplitude modulation is QAM. 9. The device of claim 1 wherein the silicon photonic device is configured to convert the output data into an output transport data in a WDM signal. 10. The device of claim 1 further comprising: a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module; a communication interface coupled to the communication block; and a control block provided on the substrate member and coupled to the communication block. 11. The device of claim 10 wherein the control block is configured to initiate a laser bias or a modulator bias. 12. The device of claim 10 wherein the control block is configured for laser bias and power control of the silicon photonics device. 13. The device of claim 10 wherein the control block is configured with a thermal tuning device or carrier tuning device each of which is configured on the silicon photonics device; wherein the SerDes block is configured to convert a first data stream. 14. A method of using a device configured for a multi-rate and selected format of data communication, method comprising: using the device comprising: a substrate member; a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol; an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, configured to convert N first data streams into M second data streams, each of the first data streams having a first predefined data rate at a first clock rate and each of the second data streams having a second predefined data rate at a second clock rate; a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block, wherein the signal processing block executes a wavelength divisional scheme to produce a data packet modulated with a multi-channel-multi-bit rate; a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking; a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in either an amplitude modulation format or a combination of phase/amplitude modulation format or a phase modulation format; a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using a loop back signal from an optical tap coupler, and configured to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface; a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module; a communication interface coupled to the communication block; and a control block provided on the substrate member and coupled to the communication block; initiating a signal from the control block to initiate a laser bias or a modulator bias; and tuning, using the control block, the silicon photonics device. 15. The method of claim 14 wherein the driver module is selected from a current drive or a voltage driver. 16. The method of claim 14 wherein the driver module is a differential driver. 17. The method of claim 14 wherein the amplified modulation format is selected from NRZ format or PAM format. 18. The method of claim 14 wherein the phase modulation format is selected from BPSK or nPSK. 19. The method of claim 14 wherein: the phase/amplitude modulation is QAM; and the silicon photonic device is configured to convert the output data into an output transport data in a WDM signal. 20. The method claim 14 further comprising a broad band source in optical communication with the receiver module.

Assignees

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Classifications

  • Switch and router aspects · CPC title

  • using wavelength multiplexing or demultiplexing · CPC title

  • Topology aspects · CPC title

  • Combination of different modulation schemes · CPC title

  • using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

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Frequently asked questions

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What does patent US9762984B2 cover?
In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to conve…
Who is the assignee on this patent?
Inphi Corp
What technology area does this patent fall under?
Primary CPC classification H04Q11/0005. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).