Temporal redundancy

Patent metadata

Field	Value
Publication number	US-9762434-B2
Application number	US-201214236572-A
Country	US
Kind code	B2
Filing date	Jul 20, 2012
Priority date	Aug 12, 2011
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

First claim

What is claimed is:

1. A circuit for coupling to inter-chip communication channels, comprising:
a first circuit to indicate whether at least one inter-chip communication channel is faulty;
a second circuit to distribute data bits associated with a faulty inter-chip communication channel to at least one non-faulty inter-chip communication channel; and
a third circuit to generate a clock signal that clocks transmission of data bits to the inter-chip communication channels, the clock signal being at an increased data rate when the first circuit indicates that at least one inter-chip communication channel is faulty,
wherein the second circuit comprises a plurality of serializers having outputs coupled to the inter-chip communication channels and inputs coupled to a number of internal data channels, wherein each of the plurality of serializers is triggered by a respective control signal that determines which of the internal data channels is coupled to the input of the respective one of the plurality of serializers.

2. The circuit of claim 1 , wherein the second circuit comprises at least one buffer to buffer data bits associated with the faulty inter-chip communication channel so as to allow the buffered data bits to be transmitted by a non-faulty inter-chip communication channel at the increased data rate.

3. The circuit of claim 1 , further comprising
a bypass circuit to bypass the second circuit when no inter-chip communication channel is faulty.

4. The circuit of claim 1 ,
wherein the third circuit includes at least one multiplier to produce a clock rate that is a multiple of a root clock rate.

5. The circuit of claim 1 , wherein the control signal is configured to toggle at a rate higher than a normal toggle rate when the respective one of the plurality of serializers is used to transmit data bits associated with the faulty inter-chip communication channel.

6. The circuit of claim 1 , further comprising
a memory to store identity information of the inter-chip communication channel.

7. A method, comprising:
receiving a first signal indicating at least one inter-chip communication channel is faulty; and
transmitting, by a plurality of serializers coupled to a number of internal data channels, data bits associated with a faulty inter-chip communication channel and data bits associated with a non-faulty inter-chip communication channel, via the non-faulty inter-chip communication channel, at an increased data rate; and
triggering a respective one of the plurality of serializers with a control signal that determines which of the internal data channels is coupled to an input of the respective one of the plurality of serializers.

8. The method of claim 7 , further comprising
receiving a second signal indicating an identity of the faulty inter-chip communication channel.

9. The method of claim 7 , further comprising
generating a clock signal corresponding to the increased data rate.

10. The method of claim 9 ,
wherein generating the clock signal comprises multiplying a root clock signal.

11. The method of claim 7 , further comprising
buffering data bits associated with the faulty inter-chip communication channel prior to transmission.

12. The method of claim 7 , further comprising
toggling the control signal at a rate higher than a normal toggle rate when the respective one of the plurality of serializers is used to transmit data bits associated with faulty inter-chip communication channel.

13. The method of claim 7 , further comprising
transmitting identity information of the faulty inter-chip communication channel to a second chip.

14. The method of claim 7 , further comprising
storing identity information of the faulty inter-chip communication channel on the chip.

15. A memory controller, comprising:
a register to store information indicating a faulty inter-chip communication channel;
a first circuit to re-associate data bits originally associated with the faulty inter-chip communication channel with one or more non-faulty inter-chip communication channels; and
a second circuit to generate a clock signal to facilitate transmission or receiving of the re-associated data bits via one or more non-faulty inter-chip communication channels at an increased data rate,
wherein the second circuit comprises a plurality of serializers having inputs coupled to a number of internal data channels, wherein each of the plurality of serializers is triggered by a respective control signal that determines which of the internal data channels is coupled to the input of the respective one of the plurality of serializers.

16. The memory controller of claim 15 , wherein the first circuit is to receive as input at least one of a failure indication signal, a failed bit signal, and an increased transmission clock signal.

17. The memory controller of claim 15 , wherein the first circuit comprises at least one buffer to buffer data bits associated with the faulty inter-chip communication channel so as to allow the buffered data bits to be transmitted by a non-faulty inter-chip communication channel at the increased data rate.

18. The memory controller of claim 15 , wherein the second circuit includes at least one multiplier to produce a clock rate that is a multiple of a root clock rate.

Assignees

• Franzon Paul D
• Wilson John
• Rambus Inc

Inventors

• Franzon Paul D
• Wilson John

Classifications

• H04L41/0686 Primary

  Additional information in the notification, e.g. enhancement of specific meta-data · CPC title

• H04L41/0659

  by isolating or reconfiguring faulty entities · CPC title

• G06F11/2007 Primary

  using redundant communication media · CPC title

• H04L41/0668

  by dynamic selection of recovery network elements, e.g. replacement by the most appropriate element after failure · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title