Multi-supply output circuit

Patent metadata

Field	Value
Publication number	US-9762242-B2
Application number	US-201514969451-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 24, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Disclosed examples include ICs and general-purpose I/O circuitry to facilitate interfacing of the IC with a variety of external circuits operating at different supply voltages, in which an integer number N supply drive circuits are individually coupled with a corresponding supply voltage node and selectively connect the corresponding supply voltage node to a general-purpose output node based on a supply drive control signal to allow programmable interfacing of individual general-purpose output pads or pins of the IC with an external circuit at the appropriate signal level.

First claim

The following is claimed:

1. An integrated circuit (IC), comprising:
a first supply voltage node to deliver a first supply voltage signal;
a second supply voltage node to deliver a second supply voltage signal;
a first output circuit, including:
a first output node to selectively provide an output signal to a first output pin of the IC according to a first data signal,
a first supply drive circuit operative in a first mode to electrically connect the first supply voltage node to the first output node, and in a second mode to electrically disconnect the first supply voltage node from the first output node, and
a second supply drive circuit operative in a first mode to electrically connect the second supply voltage node to the first output node, and in a second mode to electrically disconnect the second supply voltage node from the first output node; and

a second output circuit, wherein the first and second output circuits individually include a reset circuit to selectively place the corresponding output circuit in the second mode according to a reset input signal.

2. The IC of claim 1 ,
wherein the first supply drive circuit includes a first supply drive control input to receive a first supply drive control signal, the first supply drive circuit operative in the first mode when the first supply drive control signal is in a first state and the first data signal is in a first state, the first supply drive circuit operative in the second mode when the first supply drive control signal is in a second state or the first data signal is in a second state; and
wherein the second supply drive circuit includes a second supply drive control input to receive a second supply drive control signal, the second supply drive circuit operative in the first mode when the second supply drive control signal is in a first state and the first data signal is in a first state, the second supply drive circuit operative in the second mode when the second supply drive control signal is in a second state or the first data signal is in the second state.

3. The IC of claim 2 , further comprising a logic circuit to provide one of the first and second supply drive control signals in the first state, and to provide the other supply drive control signal in the second state.

4. The IC of claim 2 ,
wherein the second supply voltage signal is greater than the first supply voltage signal; and
wherein the IC further comprises a blocking circuit to block current flow from the first output node to the first supply voltage node when the second supply drive control signal is in the first state.

5. The IC of claim 4 , wherein the blocking circuit includes:
a first inverter, including an output, and an input receiving a first control signal, the first control signal having a first state when the first supply drive circuit is in the first mode and a different second state when the first supply drive circuit is in the second mode;
a first transistor, including a first terminal connected to the first supply voltage node, a second terminal connected to a first node, and a control terminal receiving a control voltage according to the first control signal to turn the first transistor on when the first supply drive circuit is in the first mode, and to turn the first transistor off when the first supply drive circuit is in the second mode;
a first diode, including an anode connected to the first supply voltage node, and a cathode connected to the first node;
a second transistor, including a first terminal connected to the first node, a second terminal connected to the first output node, and a control terminal connected to the output of the first inverter to turn the second transistor on when the first supply drive circuit is in the first mode, and to turn the second transistor off when the first supply drive circuit is in the second mode; and
a second diode, including an anode connected to the first output node and a cathode connected to the first node.

6. The IC of claim 2 ,
wherein the first output circuit includes:
a first AND gate, including a first input to receive the first supply drive control signal, a second input to receive the first data signal, and an output providing a first signal, and
a first level shift circuit, including an input to receive the first signal from the first AND gate, and an output to provide a first control signal, and
a first output transistor, including a first terminal coupled with the first supply voltage node, a second terminal connected to the first output node, and a control terminal to receive the first control signal to turn the first output transistor on when the first supply drive circuit is in the first mode, and to turn the first output transistor off when the first supply drive circuit is in the second mode; and

wherein the second output circuit includes:
a second AND gate, including a first input to receive the second supply drive control signal, a second input to receive the first data signal, and an output providing a second signal,
a second level shift circuit, including an input to receive the first signal from the first AND gate, and an output to provide a second control signal, and
a second output transistor, including a first terminal connected to the second supply voltage node, a second terminal connected to the first output node, and a control to receive the second control signal to turn the second output transistor on when the second supply drive circuit is in the first mode, and to turn the second output transistor off when the second supply drive circuit is in the second mode.

7. The IC of claim 6 ,
wherein the second supply voltage signal is greater than the first supply voltage signal; and
wherein the IC further comprises a blocking circuit to block current flow from the first output node to the first supply voltage node when the second supply drive control signal is in the first state.

8. The IC of claim 6 , wherein the first and second output circuits individually include a reset circuit to selectively place the corresponding output circuit in the second mode according to a reset input signal.

9. The IC of claim 1 ,
wherein the second supply voltage signal is greater than the first supply voltage signal; and
wherein the IC further comprises a blocking circuit to block current flow from the first output node to the first supply voltage node when the second supply drive control signal is in the first state.

10. The IC of claim 1 , wherein the second output circuit includes:
a second output node to selectively provide a second output signal to a corresponding second output pin of the IC according to a second data signal;
a third supply drive circuit operative in a first mode to electrically connect the first supply voltage node to the second output node, and in a second mode to electrically disconnect the first supply voltage node from the second output node; and
a fourth supply drive circuit operative in a first mode to electrically connect the second supply voltage node to the second output node, and in a second mode to electrically disconnect the second supply voltage node from the second output node.

11. The IC of claim 10 ,
wherein the first supply drive circuit includes a first supply drive control input to receive a first supply drive control signal, the first supply drive circuit operative in the first mode when the first supply drive control signal is in a first state and the first data signal is in a first state, the first supply drive circuit operative in the second mode when the first supply drive control signal is in a second state or the first data signal is in a second state;
wherein the second supply drive circuit includes a second su

Assignees

• Texas Instruments Inc
• Texas Instuments Incorporated

Inventors

• Forghani-Zadeh Hassan Pooya
• Merkin Timothy Bryan

Classifications

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title