Semiconductor device having control conductors

Patent metadata

Field	Value
Publication number	US-9762226-B2
Application number	US-201514802840-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Aug 5, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate having:
a first terminal region;
a second terminal region;
a first extension region that extends from the first terminal region towards the second terminal region;
a second extension region that extends from the second terminal region towards the first terminal region;
a channel region between the first and second extension regions;

a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region;
a first control conductor comprising an inner portion and an outer portion separated vertically from each other by an insulating layer, wherein the first control conductor overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and
a second control conductor comprising an inner portion and an outer portion separated vertically from each other by an insulating layer, wherein the second control conductor overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region,
wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor;
wherein the inner portions of the first control conductor and the second control conductor are enclosed within insulation material and the outer portions of the first control conductor and the second control conductor are exposed to an exterior of the semiconductor device; and
wherein the first control conductor has a control terminal electrically connected to the inner portion and a separate control terminal electrically connected to the outer portion and the second control conductor has a control terminal electrically connected to the inner portion and a separate control terminal electrically connected to the outer portion.

2. The semiconductor device of claim 1 , wherein the first control conductor is electrically isolated from the second control conductor within the semiconductor device.

3. The semiconductor device of claim 1 , wherein the substrate has a plane of symmetry that passes through a center of the channel region.

4. The semiconductor device of claim 1 , wherein the gate conductor overlies the channel region, a periphery of the first extension region and a periphery of the second extension region.

5. The semiconductor device of claim 1 , wherein the gate conductor and the first and second control conductors are made of a same material.

6. The semiconductor device of claim 1 , wherein the first and second control conductors are made from a different material than that of the gate conductor.

7. The semiconductor device of claim 1 , wherein the first and second control conductors each include a polysilicon layer, a metal layer, and a via connecting the polysilicon layer to the metal layer.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a transistor.

9. A circuit comprising:
the semiconductor device of claim 1 ; and
a driver circuit configured to provide:
a first control voltage to the first control conductor;
a second control voltage to the second control conductor; and
a gate control voltage to the gate conductor.

10. A capacitive voltage converter comprising the semiconductor device of claim 1 .

11. The semiconductor device of claim 1 , wherein a footprint of each inner portion of the first and second control conductor is entirely contained within a footprint of each corresponding outer portion of the first and second control conductor when viewed from above.

12. The semiconductor device of claim 1 , wherein the outer portions of the first and second control conductors overlap respective gaps between the inner portions of the first and second control conductors and the gate conductor.

13. The semiconductor device of claim 7 , wherein the respective polysilicon layers of the first and second control conductors comprise upper portions of the first and second control conductors, the respective metal layers of the first and second control conductors comprise lower portions of the first and second control conductors, and wherein the polysilicon layer at least partially overlies the metal layer.

14. The circuit of claim 9 wherein the first control voltage is the same as the second control voltage.

15. The circuit of claim 9 wherein the first control voltage is independent of the second control voltage.

16. The circuit of claim 9 , wherein the driver circuit is further configured to:
set the first control voltage to be higher than the gate control voltage during an on-state of the semiconductor device; and
set the first control voltage to one of (i) zero, (ii) a negative value or (iii) a lower voltage than the gate control voltage during an off state of the semiconductor device.

17. The circuit of claim 9 , wherein the driver circuit comprises a gate steering logic circuit that is configured to:
compare a first measured voltage at a first region of the semiconductor device with a second measured voltage at a second region of the semiconductor device;
determine a polarity of the semiconductor device, based on which of the first and second control conductors is associated with a source extension region and which is associated with a drain extension region, in accordance with the comparison; and
set the first and second control voltages for the first and second control conductors in accordance with a state of the semiconductor device and/or the polarity of the semiconductor device.

18. The capacitive voltage converter as recited in claim 10 , further comprising,
a driver circuit configured to provide:
a first control voltage to the first control conductor;
a second control voltage to the second control conductor; and
a gate control voltage to the gate conductor.

Assignees

• Nexperia BV

Inventors

• Heringa Anco
• Hijzen Erwin
• Surdeanu Radu

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/53271

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic