Self-aligned trench MOSFET and method of manufacture

Patent metadata

Field	Value
Publication number	US-9761696-B2
Application number	US-201414221012-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Apr 3, 2007
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

First claim

What is claimed is:

1. A method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
depositing a first semiconductor layer upon a semiconductor substrate, wherein the first semiconductor layer and the semiconductor substrate are doped with a first type of impurity;
doping a first portion of the first semiconductor layer with a second type of impurity;
etching a plurality of trenches in the first semiconductor layer;
forming a first dielectric layer on the wall of the plurality of trenches;
depositing a second semiconductor layer in the plurality of trenches;
forming a second dielectric layer over the second semiconductor layer in the plurality of trenches;
etching recessed mesas in the first semiconductor layer aligned by the first and second dielectric layers;
doping a second portion of the first semiconductor layer proximate the recessed mesas with a second type of impurity;
forming a plurality of source/body contact spacers above the recessed mesas aligned between the second dielectric layer in the trenches;
etching a plurality of source/body contact trenches between the source/body contact spacers, wherein the source body contact trenches extend through the second portion of the first semiconductor layer;
doping a third portion of the first semiconductor layer proximate the source/body contact trenches with the first type of impurity aligned by the source/body contact spacers; and
deposit a first metal layer in the source/body contact trenches aligned to the source/body contact spacers.

2. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 1 , wherein a first set of the plurality of trenches are substantially parallel with respect to each other and a second set of the plurality of trenches are normal-to-parallel with respect to the first set of the plurality of trenches.

3. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 1 , wherein the plurality of trenches are substantially parallel with respect to each other.

4. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1 , further comprising forming a silicide on the second semiconductor layer in the plurality of trenches.

5. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1 , wherein forming the second dielectric over the second semiconductor in the plurality of trenches comprises:
depositing the dielectric layer; and
removing excess dielectric until the first semiconductor layer is exposed and the second dielectric covers the first semiconductor layer in the plurality of trenches.

6. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 1 , wherein forming the plurality of source/body contact spacers comprises:
conformally depositing a third dielectric layer after doping the second portion of the first semiconductor layer; and
etching the third dielectric layer whereby the portions of the third dielectric layer substantially remain along vertical sides the second dielectric layer proximate the recessed mesas.

Assignees

• Vishay Siliconix

Inventors

• Li Jian
• Chen Kuo-In
• Terril Kyle

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H01L29/66734 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/456

  Electricity · mapped topic