Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9761690-B2
Application number	US-201414324092-A
Country	US
Kind code	B2
Filing date	Jul 4, 2014
Priority date	Jun 9, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate;
forming an interfacial layer on the substrate;
forming a stack structure on the interfacial layer, wherein the stack structure comprises a high-k dielectric layer, wherein the high-k dielectric layer comprises a metal oxide layer;
patterning the stack structure to form a gate structure on the interfacial layer, wherein the high-k dielectric layer is I-shaped and a width of the high-k dielectric layer and a width of the interfacial layer are different and the width of the high-k dielectric layer is taken in a horizontal direction from the substrate;
forming a liner on and contacting a top surface of the interfacial layer and the gate structure;
removing part of the liner and part of the interfacial layer for forming a first spacer; and
forming a second spacer on the sidewalls of the first spacer and the interfacial layer, wherein a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

2. The method of claim 1 , wherein the interfacial layer comprises silicon dioxide.

3. The method of claim 1 , wherein the stack structure comprises the high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a silicon layer on the BBM layer, and a hard mask on the silicon layer.

4. The method of claim 3 , wherein the BBM layer comprises TiN.

5. The method of claim 3 , wherein the silicon layer comprises amorphous silicon or polysilicon.

6. The method of claim 1 , wherein the liner comprises silicon dioxide or silicon nitride.

7. The method of claim 1 , further comprising etching back part of the liner and part of the interfacial layer for forming the spacer sitting on the interfacial layer.

8. The method of claim 1 , further comprising etching back part of the liner and part of the interfacial layer for forming the spacer so that the edge of the interfacial layer is aligned with the edge of the spacer.

9. A semiconductor device, comprising:
a substrate;
an interfacial layer on the substrate;
a gate structure on the interfacial layer, wherein the gate structure comprises a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, the patterned high-k dielectric layer is I-shaped, and a width of the patterned high-k dielectric layer and a width of the interfacial layer are different, wherein the width of the patterned high-k dielectric layer is taken in a horizontal direction from the substrate;
a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer; and
a second spacer on the sidewalls of the first spacer and the interfacial layer, wherein a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

10. The semiconductor device of claim 9 , wherein the interfacial layer comprises silicon dioxide.

11. The semiconductor device of claim 9 , wherein the gate structure comprises the patterned high-k dielectric layer, a patterned bottom barrier metal (BBM) layer on the patterned high-k dielectric layer, a patterned silicon layer on the patterned BBM layer, and a patterned hard mask on the patterned silicon layer.

12. The semiconductor device of claim 11 , wherein the patterned BBM layer comprises TiN.

13. The semiconductor device of claim 11 , wherein the patterned silicon layer comprises amorphous silicon or polysilicon.

14. The semiconductor device of claim 9 , wherein the spacer comprises silicon dioxide or silicon nitride.

15. The semiconductor device of claim 9 , wherein the width of the interfacial layer is wider than the width of the gate structure.

16. The semiconductor device of claim 9 , wherein the edge of the interfacial layer is aligned with the edge of the spacer.

17. The semiconductor device of claim 9 , further comprising a contact etch stop layer (CESL) around the second spacer, wherein a bottom surface of the CESL is lower than the planar bottom surface of the first spacer.

18. The method of claim 1 , further comprising forming a contact etch stop layer (CESL) around the second spacer, wherein a bottom surface of the CESL is lower than the planar bottom surface of the first spacer.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu
• Chiou Chun-Mao
• Hsu Shih-Chieh
• Kuo Lung-En
• Jhang You-Di
• Ke Jian-Cun

Classifications

• H01L29/513

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/66545 Primary

  Electricity · mapped topic